Nominated for continuous effort in bringing key results for the pathfinding of disruptive technologies even during the pandemic period.

In 2021, imec laid the foundation for enabling backside power delivery and signal networks, which are believed to deliver further performance gains to high-performance 3D systems on chip (3D SOCs). A possible partitioning of these high-performance 3D-SOC systems involves some or all memory macros to be placed in the top die, while the logic is placed in the bottom die. On the technology side, this can be realized by bonding the active front side of the ‘logic wafer’ to the active front side of the ‘memory wafer’. One can now think of exploiting the backside of one of these wafers for either power delivery, signal routing, or both.

Besides demonstrating the beneficial impact of this approach, imec reported progress in developing the key technology building blocks. These include processes for wafer thinning, technologies for making nano-through-silicon vias (n-TSVs) that electrically connect the backside to the front side of the device wafer, and dedicated wafer bonding solutions. In addition, the imec team investigated new methodologies to realize effective power delivery networks from the broader perspective of scaled systems – combining on-chip as well as off-chip components. These developments have been highlighted at major conferences, incl 2021 VLSI and 2021 IEDM.