In the Imec view, there are three key technology elements for 3D integration:
Through-silicon-via (TSV)
Die-to-die, die-to-wafer stacking & interconnect
Wafer-to-wafer bonding & interconnect technology.
Imec's research is showing good promise for scaling TSVs. However, vias in commercial products have remained static. The problem is the “interconnect gap.” The microbump has not caught up to the point where the TSV can be fully utilized. More aggressive scaling is necessary.
Teams at Imec have been working on improving bump density. Imec's work showed solder bump pitches down to 7µm with thermocompression bonding. The SEM images showed a technology demonstrator with four stacked die with 7µm pitch TSV bumped and interconnected. Clearly, Imec wants the industry to realize the opportunities and get microbumps up to speed with TSV technology.