2018 Edition. In
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s ICs, advanced IC packages, and PCBs. Cadence IC packaging and cross-domain co-design technologies are the de facto standards in system-level co-design and advanced IC packaging, delivering automation and accuracy to expedite the design process. In 2017, Cadence announced new capabilities to complete an integrated design flow developed earlier in collaboration with TSMC for TSMC’s advanced wafer-level Integrated Fan-Out (InFO) packaging technology. Cadence’s integrated design enablement solution includes implementation, signoff and electro-thermal analysis tools that enable concurrent multi-chip optimization for designs incorporating InFO technology. Cadence’s new Virtuoso® System Design Platform integrates the Virtuoso, Allegro®, and Sigrity™ platforms, providing the industry’s first complete flow focused on heterogeneous integration. Cadence customers can now perform package-level LVS—an industry first—and IC signoff, including system-level layout parasitic effects. Cadence and ASE recently announced a System-in-Package EDA solution that addresses the challenges of designing and verifying Fan-Out Chip-on-substrate (FoCos) multi-die packages. The solution consists of the SiP-id™ design kit, an enhanced reference flow including IC packaging and verification tools from Cadence, and a new methodology that aggregates the requirements of wafer-, package- and system-level design into a unified and automated flow.