2016 Edition. In
Mentor Graphics is the first EDA company to formalize a physical verification process for 3D packages that incorporate die from multiple processes and multiple foundries. The PV process uses Calibre® 3DSTACK, an extension of Calibre die-level signoff verification, to verify heterogeneous multi-die integration using packaging rules (from assembly houses) in an assembly design kit (ADK). Packaging rules are independent of any specific package design or die process. Not only does this ADK ensure that an IC package meets manufacturability and performance requirements, but it also supports a unified co-design flow. Mentor then expanded their solution to support design applications, like TSMC’s integrated fan-out (InFO) wafer-level packaging technology. Using Calibre physical verification tools and the Xpedition® Package Integrator flow, customers can deploy fan-out layer structures and interconnects, and view and cross-probe results within Calibre RVE inside the Xpedition Package Integrator flow for verification of interconnect structures. Implementing a repeatable, proven process using Mentor’s industry-leading tools, providers of IC packages, fan-out wafer-level packaging, and 3D systems integration can improve both their first-time success rate and overall product quality.