11/05/2020 - 11/06/2020 -12:00 am

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Now November 5-6, 2020

Discount registration fees are available until Thursday October 15, 2020.

The 3D & Chiplet Test virtual workshop is a continuation of the popular 3D TEST Workshop in conjunction with ITC / Test Week 2020.
The 3DC-TEST Workshop focuses exclusively on test of and design-for-test for three dimensional, chiplet-based, and stacked ICs (3D-SICs), including systems-in-package (SiP), package-on-package (PoP), 3D-SICs based on through-silicon vias (TSVs), micro-bumps, and/or interposers. While these stacked ICs offer many attractive advantages with respect to heterogeneous integration, small form-factor, high bandwidth and performance, and low power dissipation, there are many open issues with respect to testing such products.
The 3DC-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike. 3DC-TEST will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the IEEE Philadelphia Section in concurrence with the Test Technology Technical Council (TTTC).

3D Test Workshop Program

The workshop program contains the following elements.
  • Keynote Address: Joris Van Campenhout, Fellow Silicon Photonics and Director Optical I/O Industry-Affiliation R&D Program at imec (Belgium): ‘Silicon Photonics Chiplets for Scaling AI and the Cloud – Technology, Design, and Test’
  • Six sessions encompassing 18 paper presentations
  • A panel discussion ‘Test Challenges in the New 3D and Chiplet World’ moderated by Jan Vardeman of TechSearch International (USA)

Download the Full Program Here


You are invited to participate in the workshop. Participation requires registration and a registration fee. Workshop registration includes access to all technical sessions, Electronic Workshop Digest (containing extended abstracts, papers, slides, posters, as made available by their presenters). Online registration is available via the workshop’s website.

Further Information:
Erik Jan Marinissen – General Co-Chair
Kapeldreef 75
B-3001 Leuven, Belgium
Tel.: +1 32 16-288755
E-mail: erik.jan.marinissen@imec.be

Yervant Zorian – General Co-Chair
690 East Middlefield Road
Mountain View, CA, USA
Tel.: +1 (650) 584-7120
E-mail: yervant.zorian@synopsys.com

Bapi Vinnekota – Program Chair
270 Innovation Drive
San Jose, CA, USA
Tel.: +1 (408) 922-1072
E-mail: bapi.vinnakota@ocproject.net