The 47th Symposium on Microelectronics (IMAPS 2014) will cover three tiers of electronics: Systems and Applications; Design and related measurements; and Materials, Process and Reliability. IMAPS 2014 will feature 6 technical tracks that span the two and a half days of sessions on: Interposers & 2.5/3D Packaging; Modeling, design, test and reliability; materials and processes; advanced packaging and assembly; advanced and emerging technologies; and special sessions on packaging and system integration, as well as an Interactive Student Poster Session.
Don’t miss these 3D / Interposers sessions this October in San Diego:
TSV Materials & Processes
Chairs: Vidhya Ramachandran, Qualcomm; Sesh Ramaswami, Applied Materials
Through Silicon Vias are key enablers for 3D integration with aggressive form factor and power/performance scaling. This session will focus on continuing efforts to address challenges in areas such as yield, reliability, manufacturability and cost effectiveness of advanced TSV integration.
3D and Embedding
Chairs: Doug Shelton, Canon USA, Inc.; Woong-Sun Lee, SK Hynix, Inc.
3D and Embedded Device Technologies integrate passive and active components into versatile, efficient and compact 3D, 2.5D and Advanced Packaging designs that increase system functionality, reliability and IO density. This session addresses some of the challenges related to 3D and Embedded Device manufacturing including metrology, yield management, reliability and materials.
Chairs: Urmi Ray, Qualcomm; Kyu-oh Lee, Intel Corporation
This session will present highlights of integration challenges and solutions for interposers/3D packaging arena.
Chairs: Steve Annas, Triton MicroTech; Aric Shorey, Corning
The use of glass as a semiconductor substrate continues to mature. In this session, significant progress in development of the manufacture of glass interposers in wafer and panel format will be presented.
Interposers/3D Integration – II
Chairs: John Hunt, ASE US Inc.; Tolga Tekin, Fraunhofer IZM
Manufacturing technologies and methods used in the fabrication of 2.5D interposer and 3D silicon packaging
Advanced Interconnect Innovations
Chairs: Jeffrey Hartman, Northrop Grumman; Josh Luff, Honeywell
This session will explore applications and processes for integration and interconnect technologies.
High-end Packaging Development: Opportunities and not Challenges
As silicon scaling has reached an asymptote, Packaging is now the key driver for increasing System bandwidth and performance. With Big Data and Analytics driving business decisions, high-end mainframes form the backbone of complex Cloud-based data-centers. After tracing the history of high-end Packaging, this keynote address will describe the opportunities available at the package and System level to drive the next-generation compute models. Opportunities span new packaging form-factors, advanced materials and complex assembly processes. Underlying such development is a need for unified testing and modeling standards.
Thursday Morning –
Stacked 3D Memory Technology – Challenges And Opportunities
The appetite for higher bandwidth and lower power are driving technologists and system architects to reconsider how processors and memory can work more efficiently and with improved proximity.ybrid Memory Cube (HMC) is a new memory architecture that enables significantly higher performance and lower energy per bit. HMC incorporates 3D Silicon integration with a stacked memory and controller in a single package incorporating heterogeneous multi die stacking with Through Silicon Vias. Enabling this technology has required innovation and integration and solving several technical challenges. In this talk key enabling technologies and their challenges will be discussed. The new 3D Memories such as Hybrid Memory Cube, Wide I/O 2, and High Bandwidth Memory provide opportunities for innovation in wafer and package technology for the future.
The Future of Packaging Panel Discussion