10/18/2016 - 10/20/2016 -All Day

Location: DoubleTree by Hilton Hotel

Loading Map....

The 13th Annual International Wafer-Level Packaging Conference will take place October 18-20, 2016 in San Jose, California USA where industry leaders, technologists, and innovators will meet in the heart of Silicon Valley. With this year’s theme “Bridging the Interconnect Gap,” IWLPC emphasizes the evolution and advancements in wafer-level, 3D and MEMS technologies to meet current and future packaging requirements.

The 2016 technical program includes two exceptional keynote presentations, the first from Professor Klaus Dieter-Lang, Ph.D., Fraunhofer IZM, “Advanced Technology Platforms for Next Generation of Smart Systems,” and the second from Professor Rao Tummala, Ph.D., Georgia Institute of Technology, “Promise & Future of Embedding & Fan-out Technologies.” In addition, two timely panel discussions — one on panel-level fan-out packaging, and the second on chip/package interaction — four professional workshops, a series of interactive presentations (a first for the IWLPC), and an extensive technology exhibition round out an outstanding program for this year’s IWLPC.

Be a part of the success at this year’s IWLPC and make plans to visit Silicon Valley October 18-20, 2016.  Registration is open now.


For more information on the conference, exhibition or sponsorship opportunities, please contact:
Jenny Ng at jenny@smta.org | 952-920-7682