2017 3D InCites Awards Nominees

2017 3D InCites Awards Nominees

The nominees for the 2017 3D InCites Awards are listed below by category. Winners will be chosen by industry peers, through an online voting process. We are accepting nominations through June 20. Online voting opens June 22, 2017, and closes July 6, 2017.

Device of the Year


Is a device architecture that was developed and qualified for high volume production in record time. The announcement of its use in the A10 processor in September 2016 paved the way for fan-out applications to be used in mobile products in high volumes. It single-handedly changed market reports for FOWLP adoption.

AMD's Fiju GPU

The Fiji GPU is the first real 3D product in volume manufacturing. AMD's use of a silicon interposers with 65,000 TSVs and a logic die in the center of four HBM stacks with four DRAM each represents a major engineering achievement. the Fiji GPU has 4X bandwidth improvement per watt over AMD’s Radeon™ R9 290X. It has a 4,096-bit memory interface with four stacks creating 512GB/s of bandwidth, which is 60 percent more bandwidth than the Radeon™ R9 290X.

M-Series™, Deca Technologies

Wafer level fan-out packaging has been recognized as a technology with attributes that address many of the challenges the industry faces with more conventional approaches. M-Series addresses some of the key limitations the incumbent approaches faced courtesy of the adaptive processing combined with planar front side molding. The investment of over $110m in Deca by two of the giants of the industry is testimony to this technology.

EDA Provider of the Year

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Engineer of the Year

Ivor Barber

Ivor Barber, Corporate VP, Packaging, AMD, has enjoyed a distinguished career in engineering and engineering management, with a focus on semiconductor packaging. He has been a Senior / Staff Package Design Engineer with LSI Corporation, the Manager/Director Flip Chip Package Design and Characterization, also at LSI, and the Senior Director Package Technology Development at XILINX, in addition to other positions. Ivor is a clear and entertaining speaker who is able to convey the essence of engineering challenges in packaging to audiences of all levels, based on his extensive experience in the industry and his good sense of humor.

Minsuk Suh, SK hynix

Minsuk Suh leads the team who successfully developed and launched sk Hynix 3D hybrid memory stacks (IBM) using through silicon via technology implemented first for GPUs, paving the way for volume manufacturing in networking and HPC applications.

Dusan Petranovic

Dusan worked diligently with major foundries and OSATs to enable 2.5D and FO-WLP designs. The Mentor software he developed assures that multiple dies co-exist peacefully in an IC package. He developed a significant part of Mentor's recently announced die - package - board High Density Advanced Packaging (HDAP) design flow.

Equipment Supplier of the Year

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Manufacturer of the Year

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Materials Supplier of the Year

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Process of the Year

Adaptive Patterning, Deca Technologies

Adaptive patterning for wafer level fan-out packaging permits the shift of the die following pick and pack to be accommodated during subsequent processing thereby resolving yield issues that may occur due to the placement tolerance. A comparison would be to suggest wire bonding be accomplished with or without pattern recognition. Its efficiency results in the choice of pick and place capital to be more focused on the cost effectiveness rather than purely placement accuracy.

Direct Bond Interconnect - Invensas

DBI technology is a low-temperature hybrid wafer bonding solution that allows wafers to be bonded with exceptionally fine pitch 3D electrical interconnect without requiring bond pressure. DBI 3D interconnect can eliminate the need for thru silicon vias (TSVs) reducing die size and cost while providing a roadmap to pixel level interconnect for future generations of image sensors.


KOBUS has developped an alternative deposition method, at the crossroads of ALD and CVD: FAST for Fast Atomic Sequential Technology. It is well suited to obtain thick and conformal layers, and is able to in-situ clean reactor even with metal materials like copper for production requirements.
Based on that technology, we demonstrate a unique deposition stack for TSV application. While we keep the same materials in the stack (SiO2 for liner, TiN for barrier and Cu seed before electroplating), thick and conformal layers are obtained for next generation high aspect ratio TSV needs including: conformality tuning, high deposition rate over PEALD, low temperature deposition compatibility (down to 100°C), good adhesion properties, and excellent electrical properties. Thus we overcome the inherent limitations of actual CVD, PECVD and PVD deposition methods, and offer more flexible and much more higher throughput than ALD and PEALD processes.

4th Generation Temporary Wafer Bonding - Brewer Science

Brewer Science’s 4th generation of temporary wafer bonding technology advances a wide range of applications from fan-out wafer level packaging to emerging panel processes. This is achieved via a low bond temperature (near room temperature) and ≤ 400˚C-stable adhesion with a post-bond total thickness variation (TTV) of ≤ 5%. This technology utilizes a highly conformal thermoplastic layer with little to no melt flow over the device features and bonds it to a curable layer on the carrier wafer. The two layers do not intermix or react chemically to one another, allowing for simple debonding with either mechanical or laser release processes. Brewer Science’s Gen 4 temporary wafer bonding extends the roadmap for temporary wafer bonding while increasing throughput and yields for a broader range of devices.

Mentor Xpedition High-Density Advanced Packaging Flow

The Xpedition High-Density Advanced Packaging (HDAP) flow from Mentor, a Siemens Business, is the industry's first comprehensive solution for the design and verification of today's leading-edge IC designs. Comprising the industry-unique Xpedition Substrate Integrator tool, rapid prototyping of heterogeneous substrate package assemblies provides accurate "what-if" evaluations in hours versus days, compared to traditional tools and processes. And the new Xpedition Package Designer technology for physical package implementation ensures data synchronization for reliable design sign-off and verification. The HyperLynx technologies from Mentor are integrated with the Xpedition Package Design tool for 2.5D/3D simulation models and design rule checking (DRC) to find and correct design errors with accuracy before tape-out. Mentor's Calibre 3DSTACK technology, when integrated with the Xpedition Package Designer tool, enables complete sign-off verification for complete multi-die systems at any process node without breaking current tool flows and does not require new data formats. This results in significant time reduction to tape-out.

Research Institute of the Year

Institute of Microelectronics Singapore

Working with industry to advance electronic packaging technology for over 20 years. Most recently, established a consortium with the entire supply chain to demonstrate RDL 1st ( a.k.a chip-last) and Mold 1st (a.k.a chip-first) to extend Fan-Out WLP to 2.5D integration, Ultra-thin 3D Fan-Out, and 5G Antenna-in-Package applications. In parallel executing cost-effective panel-packaging through the Gen-3 Panel based Fan-Out Consortium.

Fraunhofer IZM

Fraunhofer IZM specializes in industry-oriented applied research. With four technology clusters, Fraunhofer IZM covers the entire spectrum of technologies and services necessary for developing reliable electronics and integrating new technology into applications. Of particular note is Fraunhofer IZM's work leading the Panel Level Processing Consortium..


CEA-LETI has been developing for a decade 3D integration, and have pursued research in both directions: developing advanced 3D technology bricks (TSVs, μ-bumps, Hybrid Bonding, etc), and designing advanced 3D circuits as pioneer prototypes.


Imec is the world-leading R&D center for nano-electronics and digital technology. As a trusted partner for companies, start-ups, and universities imec brings together close to 3,500 brilliant minds from over 70 nationalities. It leverages state-of-the-art infrastructure, such as its 200mm and 300mm wafer fabs, to perform research for a multitude of industries, including most of the top-10 semiconductor companies.

In imec’s Industrial Affiliation Program on 3D System Integration, imec’s own staff works alongside engineers from industrial partners, key suppliers, and leading academic partners towards radical innovation and pre-competitive development. In the field of 3D, imec has made ground-breaking contributions, for example in the areas of TSV processing, micro-bump interconnect and scaling, temporary and permanent die and wafer bonding, 3D design, testing and probing, design-for-test and the standardization thereof, the impact of 3D structures on FETs, thermal management, chip-package interaction, reliability, and cost modeling.

Imec is headquartered in Leuven, Belgium and has distributed R&D groups at various Flemish universities, in the Netherlands, Taiwan, USA, China, and offices in India and Japan. In 2016, imec's revenue (P&L) totaled around EUR 496M. See: www.imec.be.

Start-up of the Year

3DiS Technologies

3DiS Technologies is a young technology company that offers an innovative multi-level 3D interconnect technology (3D RDL) for the integration of miniaturized electronic systems and high performance 3D inductive passive devices.


KOBUS has developped a unique deposition technology called F.A.S.T. for Fast Atomic Sequential Technology.
Launched during Semicon Europa last year, we developped an hybrid reactor between ALD and CVD, with plasma enhanced capability.
Offering thick and conformal deposition capability at high througput and compatible with low thermal budget constraints, our technology allow us to be the best candidate to answer the future needs in thin film deposition of advanced packaging.


The Company
Founded in 2014 and based in Irvine, CA, TransSiP’s patent estate represents a portfolio of innovation in the application of advanced materials and 3D heterogeneous (active and passive) embedded system-in-package technologies to the challenge of More-than-Moore (MtM) electronic systems.

The Technology
In the power conversion space, TransSiP’s lead product JC-PFM™ is a synchronous step-down micro DC-DC converter packaged in a 3D heterogenous SiP integrating switching controller, inductor, and TransSiP’s patent-pending JC™ switching noise jitter (“SNJ”) conditioning technology.
JC™ SNJ conditioning addresses the critical problem of chaotic noise present on the regulated output voltage of pulse-frequency modulation (PFM) type switching-mode DC-DC converters. JC™ does this through recognition and reduction of the uncertainty responsible for variation in timing of events in the negative feedback control loops used to trigger the semiconductor switches in the device.

So What?
Despite conversion efficiencies ranging from 80 - 95% depending on load conditions, up to now the problem of chaotic noise and variable switching frequencies has excluded PFM DC-DC converters from use with applications sensitive to supply bias noise such as spread-spectrum wireless communications and navigation/positioning. As a result, all battery-powered devices with communication and/or positioning functionality use linear DC voltage regulation (so-called “low dropout” or “LDO”). Linear regulators don’t output switching noise on the supply bias, but operate at much lower (<5 - 60%) efficiencies. Therefore despite advances in low-power semiconductor technologies, the voltage conversion necessary to supply a stable supply bias is stuck with the same old wasteful paradigm. In addition to the limitations on autonomy, the response by LDO regulators to variable load profiles (sleep <=> full load) introduced in attempts to maximize battery life introduces transients which can impact downstream circuitry or generate errors in analog to digital data convolution. These are effectively suppressed using TransSiP’s JC™ technology in the form of their Harmony™ SNJ conditioning module.

The Bottom Line
Whether a highly efficient, integrated JC-PFM™ solution or Harmony™ conditioning of an LDO, the result is a noise-optimized supply bias for powering wireless SoCs, RF components, high precision TCXOs, ADCs and other noise sensitive RF and analog circuit elements.
Field tests using JC-PFM™ to power one of the leading sports/runner platforms have not only shown as much as a 5X increase in battery life, but have conclusively demonstrated that TransSiP’s JC™ technology provides the ability to “Run Farther, Run Better”!

Startup of the Year

This category doesn't have nominations yet