2016 3D InCites Awards Nominees

2016 3D InCites Awards Nominees

The nominees for the 2016 3D InCites Awards are listed below by category. Winners will be chosen by industry peers, through an online voting process. We are accepting nominations through June 20. Online voting opens June 22, 2016 and closes July 8, 2016.

Device of the Year

Amkor Technologies, Inc: SWIFT

SWIFT : uniquely developed to deliver a high yielding, high performance package with the thinnest profile in the industry. This package can deliver 2um line/space lithographiy with up to 4 layers of RDL and a very dense network of memory interface vias from bottom package to top package at a very cost competitive price. Due to the nature of fabrication, the package provides a path during processing for known good die to known good die site placement, virtually eliminating the risk of high value die loss during the product build. This is a key distinguishing feature that also allows for significant reduction in cycle time by fabricating the RDL prior to die arrival for assembly and also ultimately improves overall cost by maximizing the yield during fabrication.

Omnivision's PureCelPlus-S

OmniVision’s new PureCelPlus-S stacked die technology separates the imaging sensor array from the image sensor processing pipeline, supporting additional camera functionality and system level integration into smaller hardware profiles. This design leads to improved sensor performance while enabling a smaller footprint when compared with non-stacked sensors. PureCelPlus-S architecture stacks circuits in the silicon support wafers underneath image sensors, enabling advanced features such as higher dynamic range expansion, on-chip ISP noise cancellation, and fast auto focusing. OmniVision's growing portfolio of compact PureCelPlus-S sensors offer best-in-class image quality and high functionality, delivering superior low-light performance, improved dynamic range, and minimal power requirements.

Deca Technologies: • M-Series™

Conventional fan-out wafer-level packaging (FOWLP) is hampered by the cost of capital, die-attach cost, and yield. M-Series was built from the ground up to break down those barriers to adoption. M-Series features Adaptive Patterning™, a dynamic design and patterning process that resolves the issues associated with shifting die within an embedded device structure.


InFO PoP is an excellent idea as a device architecture and has been developed AND QUALIFIED for high volume production in record time. I suspect that this packaging technology will reward TSMC with significant revenues - already in 2016.

AMD's Fiju GPU

AMD's use of a silicon interposers with 65,000 TSVs and a logic die in the center of four HBM stacks with four DRAM each represents a major engineering achievement. the Fiji GPU has 4X bandwidth improvement per watt over AMD’s Radeon™ R9 290X. It has a 4,096-bit memory interface with four stacks creating 512GB/s of bandwidth, which is 60 percent more bandwidth than the Radeon™ R9 290X.

Engineer of the Year

Boyd Rodgers, VP of research and development, Deca Technologies

Boyd Rodgers led the development M-Series and its unique Adaptive Patterning technology, which addresses the die-shift issue in conventional fan-out wafer level packaging. He is a three-time winner recipient IWLPC Best Paper Awards including Best of Wafer-Level Packaging Track for his paper, “Implementation of a Fully Molded Fan-Out Packaging Technology” as well as overall Best Paper and Best of the WLP Track designations for his paper titled “Enhancing WLCSP Reliability Through Build-Up Structure Improvements and New Solder Alloys.”

Bryan Black and AMD's engineering team

AMD's use of a silicon interposers with 65,000 TSVs and a logic die in the center of four HBM stacks with four DRAM each represents a major engineering achievement. Fiji has 4X bandwidth improvement per watt over AMD’s Radeon™ R9 290X. It has a 4,096-bit memory interface with four stacks creating 512GB/s of bandwidth, which is 60 percent more bandwidth than the Radeon™ R9 290X.

The new architecture required 8.5 years of R&D, engineering, and product ramp. The massive engineering effort included technical core competence development of micro-bumping, middle-end-of-line (MEOL) TSV fabrication, assembly, and test solutions. A total of 20 different company and government organizations were involved in working on the project. Demonstrations in conjunction with the Fraunhofer Institute in Germany assisted in the development of the tool infrastructure. The complexity of die stacking involved many factors that could only be analyzed and addressed by building functional prototypes.

Dr. Peter Hartwell

Dr. Peter G. Hartwell is Senior Director of Advanced Technology at InvenSense. Peter has extensive experience in commercializing silicon MEMS products, working on advanced sensors and actuators, and specializes in MEMS testing techniques. Prior to joining InvenSense, Peter spent four years as Architect of Motion Sensing Hardware at Apple. Peter also worked as a Distinguished Technologist at Hewlett-Packard Laboratories. At HP, he was the MEMS lead on HP’s 10 nano-g/rt Hz MEMS accelerometer forming the basis of HP’s Central Nervous System for the Earth (CeNSE), an early version of what has become the Internet of Things. Peter has over 40 worldwide patents on MEMS and sensor applications. In the past year, Peter has extended his work in MEMS at InvenSense to push forth his vision to capture additional value by delivering intelligent sensors that create a more efficient system by transmitting not just raw sensor data, but rather information and context to the cloud. Thus, IoT companies will accelerate as the focus will be on applications of information rather than collection and analysis of raw sensor data. He has proven that the industry needs to build expertise in sensor intelligence, system knowledge, and even big data, in order to not just participate, but thrive, in the forthcoming Internet of Sensors.

Fabless of the Year


Nvidia developed last year the VOLTA graphics card, offering high-end graphics users one Terabyte of bandwidth ( this bandwidth fits as much as 500 4K HDTV channels !!! ). This year they took this accomplishment even a step further. They used VOLTA as the core of a server blade and completed their steps from a powerful graphics CHIP, to an impressive graphics CARD to a very competitive server blade SYSTEM.


AMD's significant accomplishment as a fabless was the development and commercialization of the Radeon Fury product line featuring the Fiji GPU, representing a number of industry "firsts": It’s the first time die stacking is used in the graphics market; it’s the first high-volume manufacturing interposer. It’s the first time TSVs with micro-bumps are used in the graphics industry, and it’s the first time 22 discrete die manufactured by different companies are integrated into one single package.

InvenSense, Inc.

InvenSense has this past year become the leading supplier of motion sensor suppliers in terms of revenue for mobile device motion sensors, according to IHS, IHS reports that InvenSense has increased its market share from 22.5% in 2014 to 30% in 2015. Moreover, InvenSense dominates the supply of combo motion sensors, with 57% market share for mobile devices. The first generations of devices employed discrete sensors, along with micro-controller based sensor hubs which performed sensor fusion with limited multi-purpose capabilities. Recent innovations lead by InvenSense in MEMS technology has enabled a new generation of sensors which integrate multiple sensors, together with CMOS processors, memory and software stack to deliver complete application specific smart sensors.

Invensas Zibond and DBI Technologies

Invensas technologies Zibond and DBI are at the forefront of enabling the adoption of wafer-to-wafer, die-to-die and die-to-wafer bonding in the volume production of image sensors, MEMS, 3D IC and other semiconductor packaging applications.

Zibond is a low temperature homogeneous (oxide to oxide) direct bonding technology that forms strong bonds between wafers or die with same or different coefficients of thermal expansion (CTE). The technology uniquely addresses the need to transfer material grown on a particular substrate, for lattice matching or process development to another substrate, for improved device performance.

DBI is a low temperature hybrid direct bonding technology that allows wafers, or die, to be bonded with exceptionally fine-pitch 3D electrical interconnect. DBI can minimize the need for Thru Silicon Vias (TSVs) and Thru Die Vias (TDVs) by forming interconnects at the bonded surface.

These advanced low temperature bonding technologies enable reduced manufacturing stress and enhance device reliability compared to other conventional bonding techniques, while also providing lower cost-of-ownership.

Foundry of the Year

This category doesn't have nominations yet

Lifetime Achievement Award

Phil Garrou

For the insights that he provided via his blog, his involvement in the IEEE 3D-IC and RTI 3D-ASIP conferences and For publishing the first series of Handbooks on 3D ICs.

Dr. Riko Radojcic

Riko was a real pathfinder in the early wilderness of 3D IC technology in both its aspects: chip architecture and design. He has influenced many folks from different areas as foundries, OSATs, EDA to start work together. Due to his inspiration and vision the development of new EDA tools have been initiated: extraction, thermal and stress assessments, etc. 3D integration survived an initial skepticism and pessimism inevitable accompanying any novel technology because of such enthusiasts as Dr. Riko Radojcic.

Madhavan Swaminathan

Madhavan Swaminathan, Ph.D. has been a very active and highly visible proponent of 3D integration. In addition to solving one of the EDA industry's top issues for 3D TSV design and simulation, he has written one of the most popular textbooks on 3D design, continues to do a large amount of research work on 3D, and is actively promoting and supporting the technology's evolution.

Professor James Lu

Dr. Lu authored and co-authored >250 publications in journals, conferences or books. He served as General Chair, Technical Chair, and Session Chair and committee members for many international conferences or workshops (such as General Chair of IMAPS International Conference on Device Packaging). He has been a panelist, panel moderator, keynote or invited speaker for many conferences, and given many seminars at government labs, universities and industrial organizations. He is listed in the special Millennium Edition of Marquis Who's Who in Science and Engineering, received many honorable awards, including the the 2008 IEEE CPMT Exceptional Technical Achievement Award "for his pioneering contributions to and leadership in 3D integration/packaging”, the IMAPS 2010 William D. Ashman Achievement Award "for contributions and research in 3D integration and packaging; for leadership contributions at international symposiums and device packaging conferences, and 3-D packaging workshops.

OSAT of the Year

Deca Technologies, Inc.

Deca’s Autoline manufacturing processes significantly reduce cycle time, thereby giving customers an ability to respond to rapid market demand swings and the competitive edge to be first to market. Deca has shipped more than .5B WLP units in three years. ASE recognized M-Series as the only viable high-volume manufacturing FOWLP solution and invested $60M in optimizing its manufacturing process and expanding production of chip-scale packages using this technology. As such, M-Series is validated as a technology that will bring FOWLP to mass production.


Amkor developed, based on the SINGLE DIE fan-out wafer-level packaging technology two cost-effective and feature-rich MULTI-DIE packaging families: SLIM and SWIFT.


The significant achievement is their shipping 1B+ FOWLP devices to date, with an emphasis on being able to advance heterogeneous integration in a very cost-effective way: STATS ChipPAC Pte. Ltd. has shipped over one billion fan-out wafer level packages (FOWLP), also known in the industry as embedded Wafer Level Ball Grid Array (eWLB). FOWLP or eWLB is an advanced packaging technology platform that provides ultra-high density interconnection, superior electrical performance and the ability to integrate multiple heterogeneous dies in a cost-effective, low-profile semiconductor package.


NANIUM' is a world-class provider of advanced semiconductor packaging, assembly, and test, engineering and manufacturing services. The company is a leader in 300mm Wafer-Level Packaging (WLP), both Fan-In/ WLCSP, but mainly Fan-Out/ WLFO based on eWLB technology. NANIUM is well recognized in the packaging community worldwide and was awarded by several of its customers and co-operation partners emphasizing the high level of engineering and innovation creating leading edge packaging solutions such as FOWLP based WLSiP and WL3D. NANIUM is the largest OSAT in Europe and strongly engaged in activities strengthening this part of the Semiconductor Supply Chain. NANIUM is co-founder and chair of the ESiPAT Group (European SEMI integrated Packaging, Assembly and Test Special Interest Group).

Research Institute of the Year


CEA Leti has a track record of driving visionary research.
The latest such program is well known as the COOL-CUBE, a monolithic integration of two (in future even more) layers of circuitry vertically stacked. As wafer-fab experts can tell you, running a wafer again multiple times through fab, after you finished processing all the diffusion and metal layers needed manufacture a wafer with typical SoC circuitry, is very challenging. It takes special recipes and very careful processing to NOT ruin transistor performance on the first layer, while adding the second layer on top of it.

Institute of Microelectronics Singapore

Working with industry to establish consortium with entire supply chain to enable early demonstration of RDL 1st ( a.k.a die-last) FOWLP for mobile and tablet applications.

Fraunhofer Cluster for 3D Integration

The Fraunhofer Cluster for 3D Integration is represented by the Fraunhofer IZM-ASSID, Fraunhofer ENAS, Fraunhofer IIS/EAS, Fraunhofer IKTS, Fraunhofer IPMS

… for their fundamental work in 3D Heterogeneous Integration for the realization of Smart System in Package in the era of Internet of Things (IoT). Each institute in the cluster delivers a holistic approach to the design, development, and implementation of 3D heterogeneous systems for industrial applications from demonstrator development up to prototyping and low-volume manufacturing

The Fraunhofer 3D Cluster looks at the system from all perspectives from functionality, design, technology, performance and reliability and provide an integrated solution as a system integrator. The complete value chain is available inside the cluster to serve the customer for a successful 3D solution. The cluster is also involved in various projects supported by the European commission e.g. MASTER 3D, CarrICool, ADMONT – each institute bringing its very own expertise into the project and in this way generating valuable synergies to create and validate new technical and technological solutions.

Supplier of the Year

SPTS Technologies

SPTS Technologies provides plasma etch and deposition solutions that have enabled many of the recent advances in 2.5D/ 3D integration, and continually promotes advanced packaging technologies through active participation in industry consortia and events. Working closely with renowned research institutes and production customers around the world, including leading device manufacturers, foundries and OSATs, SPTS plays a leading role in delivering wafer processing technologies for today’s HVM manufacturers and for the developers of tomorrow’s solutions. SPTS’s deep silicon etch expertise for through-silicon via (TSV) etching offers market-leading etch rates and low tilt. The same hardware carries unique end-point technology to control TSV reveal in volume manufacture, and is also being used by imec for extreme wafer thinning on future multi-stack applications. We also offer low temperature PECVD for dielectric deposition onto standard, bonded or fan-out wafers, and most recently our Sigma® PVD system with an integrated multi-wafer degas and specially designed pre-clean module has been instrumental in enabling the industry-wide transition of FOWLP from a niche packaging technique for small devices to a mainstream high density architecture for high value chips.

Mentor Graphics

Mentor Graphics is the first EDA company to formalize a physical verification process for 3D packages that incorporate die from multiple processes and multiple foundries. The PV process uses Calibre® 3DSTACK, an extension of Calibre die-level signoff verification, to verify heterogeneous multi-die integration using packaging rules (from assembly houses) in an assembly design kit (ADK). Packaging rules are independent of any specific package design or die process. Not only does this ADK ensure that an IC package meets manufacturability and performance requirements, but it also supports a unified co-design flow. Mentor then expanded their solution to support design applications, like TSMC’s integrated fan-out (InFO) wafer-level packaging technology. Using Calibre physical verification tools and the Xpedition® Package Integrator flow, customers can deploy fan-out layer structures and interconnects, and view and cross-probe results within Calibre RVE inside the Xpedition Package Integrator flow for verification of interconnect structures. Implementing a repeatable, proven process using Mentor’s industry-leading tools, providers of IC packages, fan-out wafer-level packaging, and 3D systems integration can improve both their first-time success rate and overall product quality.

Dow Electronic Materials

As a global supplier of advanced semiconductor packaging materials, Dow Electronic Materials’ broad platform provides innovative solutions for metallization, dielectrics, lithography and bonding applications. The most significant achievement over the past year was the introduction of SOLDERON™ BP TS 6000 Tin-Silver, which has rapidly become the leading lead-free solder chemistry for advanced packaging applications. Tin-silver is essential for reliably capping copper pillars, particularly as higher I/O counts and tighter pitches become the norm. No other commercially available solder chemistry has met this tin-silver performance and reliability from a single formulation. SOLDERON BP Tin-Silver is proven in HVM with excellent process flexibility, especially with its wide plating speed range and the tunable nature of silver composition. This is just one example of how Dow Electronic Materials is focusing innovation on addressing key technical challenges in the advanced semiconductor packaging market.

Invensas (A Tessera Company)

Invensas Corporation operates as a subsidiary of Tessera Technologies Inc. With this year's acquisition of Ziptronix Technology and the integration of its DBI® process into the Invensas product line, Invensas now offers the industry’s highest density, smallest footprint, lowest profile and lowest cost 2.5D and 3D IC integration platform to address the upcoming 2.5/3D-IC market growth. DBI is a low-temperature hybrid bonding technology with interconnect capability with the potential to be the industry’s finest pitch, thinnest and lowest total cost-of-ownership 3D integration solution for wafer stacking and Die-to-wafer 3D stacking using low-cost metallic materials such as Cu without micro-bumping. It eliminates micro-bumping and significantly reduces the cost of 2.5D and 3D production. Finer bond lines achieved using DBI® also helps to reduce device footprint, which can lead to increased productivity.