2017 3D InCites Awards Nominees

2017 3D InCites Awards Nominees

The nominees for the 2017 3D InCites Awards are listed below by category. Winners will be chosen by industry peers, through an online voting process. We are accepting nominations through June 20. Online voting opens June 22, 2017, and closes July 6, 2017.

Device of the Year

InFO PoP

Is a device architecture that was developed and qualified for high volume production in record time. The announcement of its use in the A10 processor in September 2016 paved the way for fan-out applications to be used in mobile products in high volumes. It single-handedly changed market reports for FOWLP adoption.

AMD's Fiju GPU

The Fiji GPU is the first real 3D product in volume manufacturing. AMD's use of a silicon interposers with 65,000 TSVs and a logic die in the center of four HBM stacks with four DRAM each represents a major engineering achievement. the Fiji GPU has 4X bandwidth improvement per watt over AMD’s Radeon™ R9 290X. It has a 4,096-bit memory interface with four stacks creating 512GB/s of bandwidth, which is 60 percent more bandwidth than the Radeon™ R9 290X.

M-Series™, Deca Technologies

Wafer level fan-out packaging has been recognized as a technology with attributes that address many of the challenges the industry faces with more conventional approaches. M-Series addresses some of the key limitations the incumbent approaches faced courtesy of the adaptive processing combined with planar front side molding. The investment of over $110m in Deca by two of the giants of the industry is testimony to this technology.


Engineer of the Year

Ivor Barber

Ivor Barber, Corporate VP, Packaging, AMD, has enjoyed a distinguished career in engineering and engineering management, with a focus on semiconductor packaging. He has been a Senior / Staff Package Design Engineer with LSI Corporation, the Manager/Director Flip Chip Package Design and Characterization, also at LSI, and the Senior Director Package Technology Development at XILINX, in addition to other positions. Ivor is a clear and entertaining speaker who is able to convey the essence of engineering challenges in packaging to audiences of all levels, based on his extensive experience in the industry and his good sense of humor.

Minsuk Suh, SK hynix

Minsuk Suh leads the team who successfully developed and launched sk Hynix 3D hybrid memory stacks (IBM) using through silicon via technology implemented first for GPUs, paving the way for volume manufacturing in networking and HPC applications.

Dusan Petranovic

Dusan worked diligently with major foundries and OSATs to enable 2.5D and FO-WLP designs. The Mentor software he developed assures that multiple dies co-exist peacefully in an IC package. He developed a significant part of Mentor's recently announced die - package - board High Density Advanced Packaging (HDAP) design flow.


Fabless of the Year

Qualcomm Technology

Qualcomm continues to drive advanced packaging progress for mobile applications in its quest for ever-smaller form factors and ever-higher levels of integration, at a variety of price points using fan-out, silicon interposers, and other cutting-edge technologies.

ZiBond and DBI - Invensas, a subsidiary of Xperi

Invensas Technologies' ZiBond and DBI are at the forefront of enabling the adoption of wafer-to-wafer, die-to-die and die-to-wafer bonding in the volume production of CMOS image sensors, RF, MEMS, 3D IC and other semiconductor packaging applications.

ZiBond is a low temperature homogeneous (oxide to oxide) direct bonding technology that forms strong bonds between wafers or die with same or different coefficients of thermal expansion (CTE). The technology uniquely addresses the need to transfer material grown on a particular substrate, for lattice matching or process development to another substrate, for improved device performance.

DBI is a low temperature hybrid direct bonding technology that allows wafers, or die, to be bonded with exceptionally fine-pitch 3D electrical interconnect. DBI can minimize the need for Thru Silicon Vias (TSVs) and Thru Die Vias (TDVs) by forming interconnects at the bonded surface.

These advanced low temperature bonding technologies enable reduced manufacturing stress and enhance device reliability compared to other conventional bonding techniques, while also providing lower cost-of-ownership.

Tezzaron Semiconductor

A pioneer in 3D IC technologies using through silicon via technology, Tezzaron Semiconductor has disrupted the semiconductor industry by requiring a whole new set of floor planning and architectures, new design tools, new structures, and new test methods. As such it is forming a family of partners and licencees who together will become the Di3D™ ecosystem; the place where the high-performance world will meet to raise the bar. Tezzaron’s Di3D™ (Dis-Integrated 3D™) technology is a direct attack on the most fundamental problems we face as an industry; transistor density, interconnect power, Interconnect delay and cost. We believe Di3D can be used to continue to drive forward on performance and value for both silicon foundries, product developers and customers.


Foundry of the Year

GLOBALFOUNDRIES

GLOBALFOUNDRIES' advanced packaging and test solutions provide a direct path to power, performance, cost and form-factor optimized solutions. Capabilities include:
Novel wafer-level fan-out solutions (HD-FO)
Non-monolithic integrated solutions (2.5/3D)◦2.5D silicon interposers
High bandwidth memory / Advanced memory integration with stacked memories
Integrated on interposer, parallel interface
Hybrid memory cube (standalone memory, serial interface)

◦3D TSV at advanced nodes

Novati Technologies

In addition to interposers, Novati is the first open-platform, full-line foundry in the world offering 3D wafer stacking services and test. Novati licensed the Ziptronix patents for direct bonding technology, ZiBond® and DBI®. With DBI®, which contains interconnect at the bond interface, Novati provides technologically advanced products in markets at a lower cost, lower power and better performance compared to competing 2.5D/3D technologies.

TSMC

From its chip-on-wafer-on-substrate (CoWoS) packaging technology to its integrated fan-out package on package (InFO POP), TSMC was the first silicon foundry to embrace the concept that advanced packaging technologies provide a solid path forward for advanced semiconductor technologies.


Lifetime Achievement Award

Tim Olson, CTO, Deca Technologies

Tim Olson has for many years been recognized and respected as a visionary in the semiconductor packaging industry. Having spent several years leading R&D with Amkor Technology Tim saw an opportunity to revolutionize the industry in wafer level packaging going outside of the customary thinking to adopt approaches having proved highly successful for SunPower in the solar industry, this led to the creation of Deca Technologies. His vision saw the growth in fan-out packaging and the need to address some of the key issues inherent in the incumbent approaches, M-Series fan-out packaging is the result of this and has been endorsed courtesy of the $111m investment by two of the industries giants.

Beth Keser

As IEEE Spectrum wrote in July 2016, Beth Keser is an established professional, an IEEE senior member, and a principal engineer in electronic packaging for Qualcomm Technologies. Dr. Keser's bio needs an update to include her role now at Intel as Director, Package Engineering, at Intel in Munich; Dr. Keser's accomplishments also include her significant contributions to fan-out packaging, both from the engineering side and from the education side, where she has so generously devoted her time and energy teaching seminars and short courses on the fundamentals of fan-out.

Rao Tummala

Professor Rao Tummala is a Distinguished and an Endowed Chair Professor in Electrical and Computer Engineering and in Materials Science and Engineering at Georgia Tech. He was the Director of IBM ’s Advanced Packaging Research laboratory responsible for IBM ’s Strategy and Programs in the U.S. , Europe and Japan before accepting a research center directorship at the Georgia Institute of Technology in 1993. Prior to joining Georgia Tech, Prof. Tummala was a Fellow at IBM Corporation where he invented a number of major technologies for IBM's products. During the last 10 years, Rao pionnered the System on Package (SOP) and vertical integration on glass substrate.

Dr. Paul Enquist

Dr. Paul Enquist, Vice President of 3D R&D at Invensas, a subsidiary of Xperi, and co-founder of Ziptronix, Inc.

For more than 30 years, Dr. Paul Enquist has been a pioneer in developing cutting edge semiconductor technologies related to high speed devices and circuits, low temperature direct bonding and 3D integration, which have been commercially adopted in more than one billion semiconductor devices, including Sony CMOS image sensors and IO Semiconductor RF front end antenna switch, now part of Qualcomm.

With more than 40 issued U.S. patents to his name, Paul is one of the industry’s pioneers in the development of 3D transistors, including devices and methods of manufacturing. Paul also spearheaded R&D efforts on bonding technologies integral to the development of devices and manufacturing methods of 3D circuits.

As a co-founder and CTO of Ziptronix, Paul was a key inventor of ZiBond and Direct Bond Interconnect (DBI) - fundamental technologies enabling the world's most advanced 3D stacked CMOS image sensors and RF antenna switch shipping in multiple generations of smartphones around the world. These platform technologies are now migrating into a wide range of other high volume semiconductor applications including MEMS, RF SAW and BAW filters, fingerprint sensors, memory and SoC, among others, and are poised to be the interconnect foundation of future 3D electronics, allowing the industry to scale beyond Moore's Law.

Under Paul’s guidance, Ziptronix was acquired by Xperi in 2015. Since the acquisition, Paul has been instrumental in accelerating the further development and adoption of 3D bonding technologies.

Paul holds Ph.D. and M.S. degrees in Electrical Engineering from Cornell University and a B.S. degree in Engineering from Columbia University. He is an IEEE senior member, member of Tau Beta Pi and Eta Kappa Nu.

Eric Beyne

Dr. Eric Beyne is the Program Director of imec's 3D System Integration program in which imec’s own staff works alongside engineers from 30+ industrial partners (IDMs, foundries, fabless semiconductor companies, and OSATs), key equipment, material, and software tool suppliers, and leading academic partners toward radical innovation and pre-competitive development. Under leadership of Beyne, this large team performs R&D in the field of high-density interconnection and packaging techniques focused on “system-in-a-package” integration, 3D-interconnections including through-silicon vias, micro-bumps, and copper pillars, wafer-level packaging, RF front-end design and technology using integrated passives and RF-MEMS, as well as research on packaging reliability including thermal and thermo-mechanical characterization.

Eric Beyne obtained an MSc degree in Electrical Engineering in 1983 and a PhD in Applied Sciences in 1990, both from the University of Leuven (KU Leuven). He has been with imec since 1986 and holds the prestigious title of imec Fellow. He has been active member of the IEEE-CPMT BOG, the IMAPS-Benelux and IMAPS-Europe Liaison committee. He received the 2016 European Semiconductor Award from SEMI Europe.


OSAT of the Year

STATS ChipPAC

STATS ChipPAC Pte. Ltd. has shipped over one billion fan-out wafer level packages (FOWLP), also known in the industry as embedded Wafer Level Ball Grid Array (eWLB). FOWLP or eWLB is an advanced packaging technology platform that provides ultra-high density interconnection, superior electrical performance and the ability to integrate multiple heterogeneous dies in a cost-effective, low-profile semiconductor package.

NANIUM S.A.

NANIUM S.A. is a world-class provider of semiconductor assembly, packaging, test, engineering and manufacturing services. The company started as Siemens Semiconductors back in 1996 and nowadays is a leader in 300mm Wafer-Level Packaging , both Fan-In/WLCSP and Fan-Out/WLFO. NANIUM offers in-house capabilities for the entire development chain, from design to multiple Wafer-Level Packaging technologies, and the flexibility to tailor and test solutions that respond to the most demanding customer requirements. In recognition of NANIUM's market-leading role in fan-out, Amkor Technology announced in early 2017 that it will acquire NANIUM to enhance Amkor’s position as one of the leading providers of WLP and WLFO packaging solutions.

J-Devices, Inc.

J-Devices is the world leader in automotive IC packaging and has long-standing relationships with the largest automotive companies and automotive components manufacturers, providing customers access to the Japanese market. J-Devices has a strong turnkey manufacturing presence throughout Japan, offering package development, package assembly, wafer probe and final test. J-Devices is equipped with a large installed test base with burn-in and 100% automated x-ray infrastructure capability. A broad package portfolio and Cu wire technology make J-Devices an ideal OSAT partner for the automotive market.


Process of the Year

Adaptive Patterning, Deca Technologies

Adaptive patterning for wafer level fan-out packaging permits the shift of the die following pick and pack to be accommodated during subsequent processing thereby resolving yield issues that may occur due to the placement tolerance. A comparison would be to suggest wire bonding be accomplished with or without pattern recognition. Its efficiency results in the choice of pick and place capital to be more focused on the cost effectiveness rather than purely placement accuracy.

Direct Bond Interconnect - Invensas

DBI technology is a low-temperature hybrid wafer bonding solution that allows wafers to be bonded with exceptionally fine pitch 3D electrical interconnect without requiring bond pressure. DBI 3D interconnect can eliminate the need for thru silicon vias (TSVs) reducing die size and cost while providing a roadmap to pixel level interconnect for future generations of image sensors.

F.A.S.T. by KOBUS

KOBUS has developped an alternative deposition method, at the crossroads of ALD and CVD: FAST for Fast Atomic Sequential Technology. It is well suited to obtain thick and conformal layers, and is able to in-situ clean reactor even with metal materials like copper for production requirements.
Based on that technology, we demonstrate a unique deposition stack for TSV application. While we keep the same materials in the stack (SiO2 for liner, TiN for barrier and Cu seed before electroplating), thick and conformal layers are obtained for next generation high aspect ratio TSV needs including: conformality tuning, high deposition rate over PEALD, low temperature deposition compatibility (down to 100°C), good adhesion properties, and excellent electrical properties. Thus we overcome the inherent limitations of actual CVD, PECVD and PVD deposition methods, and offer more flexible and much more higher throughput than ALD and PEALD processes.

4th Generation Temporary Wafer Bonding - Brewer Science

Brewer Science’s 4th generation of temporary wafer bonding technology advances a wide range of applications from fan-out wafer level packaging to emerging panel processes. This is achieved via a low bond temperature (near room temperature) and ≤ 400˚C-stable adhesion with a post-bond total thickness variation (TTV) of ≤ 5%. This technology utilizes a highly conformal thermoplastic layer with little to no melt flow over the device features and bonds it to a curable layer on the carrier wafer. The two layers do not intermix or react chemically to one another, allowing for simple debonding with either mechanical or laser release processes. Brewer Science’s Gen 4 temporary wafer bonding extends the roadmap for temporary wafer bonding while increasing throughput and yields for a broader range of devices.

Mentor Xpedition High-Density Advanced Packaging Flow

The Xpedition High-Density Advanced Packaging (HDAP) flow from Mentor, a Siemens Business, is the industry's first comprehensive solution for the design and verification of today's leading-edge IC designs. Comprising the industry-unique Xpedition Substrate Integrator tool, rapid prototyping of heterogeneous substrate package assemblies provides accurate "what-if" evaluations in hours versus days, compared to traditional tools and processes. And the new Xpedition Package Designer technology for physical package implementation ensures data synchronization for reliable design sign-off and verification. The HyperLynx technologies from Mentor are integrated with the Xpedition Package Design tool for 2.5D/3D simulation models and design rule checking (DRC) to find and correct design errors with accuracy before tape-out. Mentor's Calibre 3DSTACK technology, when integrated with the Xpedition Package Designer tool, enables complete sign-off verification for complete multi-die systems at any process node without breaking current tool flows and does not require new data formats. This results in significant time reduction to tape-out.


Research Institute of the Year

Institute of Microelectronics Singapore

Working with industry to advance electronic packaging technology for over 20 years. Most recently, established a consortium with the entire supply chain to demonstrate RDL 1st ( a.k.a chip-last) and Mold 1st (a.k.a chip-first) to extend Fan-Out WLP to 2.5D integration, Ultra-thin 3D Fan-Out, and 5G Antenna-in-Package applications. In parallel executing cost-effective panel-packaging through the Gen-3 Panel based Fan-Out Consortium.

Fraunhofer IZM

Fraunhofer IZM specializes in industry-oriented applied research. With four technology clusters, Fraunhofer IZM covers the entire spectrum of technologies and services necessary for developing reliable electronics and integrating new technology into applications. Of particular note is Fraunhofer IZM's work leading the Panel Level Processing Consortium..

CEA-Leti

CEA-LETI has been developing for a decade 3D integration, and have pursued research in both directions: developing advanced 3D technology bricks (TSVs, μ-bumps, Hybrid Bonding, etc), and designing advanced 3D circuits as pioneer prototypes.

imec

Imec is the world-leading R&D center for nano-electronics and digital technology. As a trusted partner for companies, start-ups, and universities imec brings together close to 3,500 brilliant minds from over 70 nationalities. It leverages state-of-the-art infrastructure, such as its 200mm and 300mm wafer fabs, to perform research for a multitude of industries, including most of the top-10 semiconductor companies.

In imec’s Industrial Affiliation Program on 3D System Integration, imec’s own staff works alongside engineers from industrial partners, key suppliers, and leading academic partners towards radical innovation and pre-competitive development. In the field of 3D, imec has made ground-breaking contributions, for example in the areas of TSV processing, micro-bump interconnect and scaling, temporary and permanent die and wafer bonding, 3D design, testing and probing, design-for-test and the standardization thereof, the impact of 3D structures on FETs, thermal management, chip-package interaction, reliability, and cost modeling.

Imec is headquartered in Leuven, Belgium and has distributed R&D groups at various Flemish universities, in the Netherlands, Taiwan, USA, China, and offices in India and Japan. In 2016, imec's revenue (P&L) totaled around EUR 496M. See: www.imec.be.


Start-up of the Year

3DiS Technologies

3DiS Technologies is a young technology company that offers an innovative multi-level 3D interconnect technology (3D RDL) for the integration of miniaturized electronic systems and high performance 3D inductive passive devices.

KOBUS

KOBUS has developped a unique deposition technology called F.A.S.T. for Fast Atomic Sequential Technology.
Launched during Semicon Europa last year, we developped an hybrid reactor between ALD and CVD, with plasma enhanced capability.
Offering thick and conformal deposition capability at high througput and compatible with low thermal budget constraints, our technology allow us to be the best candidate to answer the future needs in thin film deposition of advanced packaging.

TransSiP

The Company
Founded in 2014 and based in Irvine, CA, TransSiP’s patent estate represents a portfolio of innovation in the application of advanced materials and 3D heterogeneous (active and passive) embedded system-in-package technologies to the challenge of More-than-Moore (MtM) electronic systems.

The Technology
In the power conversion space, TransSiP’s lead product JC-PFM™ is a synchronous step-down micro DC-DC converter packaged in a 3D heterogenous SiP integrating switching controller, inductor, and TransSiP’s patent-pending JC™ switching noise jitter (“SNJ”) conditioning technology.
JC™ SNJ conditioning addresses the critical problem of chaotic noise present on the regulated output voltage of pulse-frequency modulation (PFM) type switching-mode DC-DC converters. JC™ does this through recognition and reduction of the uncertainty responsible for variation in timing of events in the negative feedback control loops used to trigger the semiconductor switches in the device.

So What?
Despite conversion efficiencies ranging from 80 - 95% depending on load conditions, up to now the problem of chaotic noise and variable switching frequencies has excluded PFM DC-DC converters from use with applications sensitive to supply bias noise such as spread-spectrum wireless communications and navigation/positioning. As a result, all battery-powered devices with communication and/or positioning functionality use linear DC voltage regulation (so-called “low dropout” or “LDO”). Linear regulators don’t output switching noise on the supply bias, but operate at much lower (<5 - 60%) efficiencies. Therefore despite advances in low-power semiconductor technologies, the voltage conversion necessary to supply a stable supply bias is stuck with the same old wasteful paradigm. In addition to the limitations on autonomy, the response by LDO regulators to variable load profiles (sleep <=> full load) introduced in attempts to maximize battery life introduces transients which can impact downstream circuitry or generate errors in analog to digital data convolution. These are effectively suppressed using TransSiP’s JC™ technology in the form of their Harmony™ SNJ conditioning module.

The Bottom Line
Whether a highly efficient, integrated JC-PFM™ solution or Harmony™ conditioning of an LDO, the result is a noise-optimized supply bias for powering wireless SoCs, RF components, high precision TCXOs, ADCs and other noise sensitive RF and analog circuit elements.
Field tests using JC-PFM™ to power one of the leading sports/runner platforms have not only shown as much as a 5X increase in battery life, but have conclusively demonstrated that TransSiP’s JC™ technology provides the ability to “Run Farther, Run Better”!


Supplier of the Year

UnitySC

UnitySC's TMap Fan-Out metrology solution enabled FOWLP manufacturers to better understand their process and manage their yields. TMap Fan-Out is a single metrology tool solution for Fan-Out Wafer Level Packaging from molding process start to interconnect completion. It provides accurate measurement even under extreme warp condition. Unique on the market, it can provide a full stack thickness measurement in one single step, including PI on mold compound. UnitySC shipped multiple TMap Fan-Out to leading foundries, OSAT and IDMs in 2016.

UnitySC is an advanced process control company developing, manufacturing and marketing metrology and inspection solutions for heterogenous integration. UnitySC was launched in July 2016, combining FOGALE nanotech Group’s acquired Altatech assets with the former FOGALE Semicon division.

Rudolph Technologies, Inc.

The Rudolph JetStep S Lithography System for fan-out panel-based advanced packaging processes is used to produce system-in-package (SiP) products that combine sensor, processor and memory functions for the automotive industry.

SiP is ideally suited for panel manufacturing; the JetStep S System has the ability to process very large panel sizes up to 650mm x 720mm and its large field size that optimizes throughput for larger packages.

Increasingly, a number of manufacturers are investing in panel processing technology across a variety of applications, including SiP and large die processing for multiple high-end technologies. The JetStep system’s unique combination of imaging and handling capabilities is helping early adopters more quickly prove out the cost of ownership benefits of panel processing.

Brewer Science

Since 1981, Brewer Science has provided the market with advanced materials that both broaden and extend industry roadmaps. Brewer Science’s wafer-level packaging materials have enabled device manufacturers and assemblers to reduce the form factor and increase the efficiency of their products. Spearheading the temporary wafer bonding market with its chemical release platform in 2004, Brewer Science has had multiple generations of products that have increased throughput, performance, and yield rates. From chemical to thermal slide, and today with mechanical and laser release systems, Brewer Science is committed to solving the foremost challenges in the Compound Semiconductor, 2.5D, 3DIC, and Fan-out Packaging market spaces.

Lam Research

Lam’s Syndion® is the best-in-class system for deep silicon etch, with advanced chamber technology enabling high performance with excellent productivity. It supports a range of cutting-edge applications for both CMOS image sensor (CIS) and through-silicon via (TSV) markets.

Key requirements for deep silicon etch processes are to simultaneously deliver high etch rates, excellent uniformity (both across-wafer and depth), smooth sidewalls, and low sidewall damage.

Lam’s Syndion etch system offers differentiated capabilities that allow for:
• Fast switching between phases of the rapid alternating process (RAP), higher etch rates, better depth uniformity, and smoother sidewalls
• Advanced gas distribution and center-to-edge tuning to enhance across-wafer uniformity
• Advanced productivity, leveraging Lam’s market leadership in the conductor etch space (e.g., success of Lam’s Kiyo etch product family)

With a library of technical solutions, a history of collaboration, and an active roadmap to support customers’ most stringent requirements, Syndion sets benchmarks for etch uniformity and productivity at top CIS customers for critical deep trench isolation (DTI) etch and at memory customers for TSV etch.

With leading market share for both CIS and TSV critical deep silicon etch, Lam’s Syndion is considered to be the lowest-risk deep silicon etch solution available today.

Mentor, A Siemens Business

Introduction of a supply chain focused program whose goal is to jump-start the OEM/design industries ability to adopt the latest IC Packaging technologies. By creating an open, no cost program, the World's OSATs can now get access to state of the art design tools, technical expertise and expert support to help them define and build design flow, Assembly Design Kits and Process Design Kits that will be made public their customers. This OSAT Alliance program and its members outputs will help IC design companies and their designers explore the latest Packaging technologies with the lowest risk possible.

FormFactor, Inc.

Testing for manufacturing defects is considered one of the major challenges for the various types of 3D ICs, including FOWLPs, 2.5D-SICs, and 3D-SICs. Testing itself is a cost-adder, but not testing during the stack assembly flow proves to be even more costly.

FormFactor, Inc. of Livermore, CA provides the industry’s broadest range of wafer test technologies and expertise. FormFactor is the world’s leading supplier of probe cards, and with the recent acquisition of Cascade Microtech, Inc. of Beaverton, OR, they are now also the world’s leading supplier of engineering probe stations. Through both their advanced probe card technologies as well as through their advanced probe stations, FormFactor and Cascade Microtech have greatly contributed to enable testing 3D ICs during crucial moments in the stack assembly flow.

• FormFactor has developed advanced probe cards that were used to test the High Bandwidth Memory (HBM2) DRAMs of SK hynix that were part of AMD’s Radeon R9 Fury GPU product. This is one of the world’s first 3D-SICs produced in high volume, consisting of an AMD processor and four SK hynix HBM2 DRAM stacks on top of a silicon interposer. FormFactor’s MEMS-type probe cards were key in achieving ‘known-good stacks’ (see https://doi.org/10.1109/MDAT.2016.2624282).

• Cascade Microtech’s CM300 probe station was used in conjunction with Cascade Microtech’s Pyramid Probe® technology to probe and test large arrays of fine-pitch micro-bumps. Wafers from research institute imec with micro-bump arrays compliant to the JEDEC standards Wide-I/O (1,200 micro-bumps at 50/40µm pitch) and Wide-I/O2 (1,752 micro-bumps at 40µm pitch) were successfully probed. The contact resistance was within specification, the small probe marks did not have any negative impact on stacking yield, and cost-modeling studies underlined the cost effectiveness of this approach. This work was recently awarded with the National Instruments Engineering Impact Award 2017 in the category ‘Electronics & Semiconductor’ (see http://sine.ni.com/cs/app/doc/p/id/cs-17384#).

• Cascade Microtech’s CM300 probe station has an AlignChip software function that allows to correct small misalignments prior to probing a die. Imec has used this functionality to automatically probe and test die-to-die stacks that were pick-n-placed in a matrix structure on a tape frame or on thermal-release tape (see https://doi.org/10.1109/TEST.2015.7342412).

• Cascade Microtech’s CM300 probe station also has the capability to load large tape frames, for example to test thinned-down wafers with exposed TSVs. Combined with FormFactor’s low-force probe cards, imec has demonstrated that wafers as thin as 50µm can be reliably probed.

SPTS Technologies Ltd

SPTS Technologies provides plasma etch and deposition equipment which has enabled many of the recent advances in 2.5/3D integration. Working on leading edge technologies with renowned research institutes, and helping to implement the best processes at leading device manufacturers, foundries and OSATs, SPTS has been at the forefront of developing a number of key wafer processing techniques and transferring these into full scale production.

Notable contributions include high productivity PVD of UBM/RDL for FOWLP with multi-wafer degas to double wafer throughput and reduce Rc, and a new pre-clean etch module to reduce contaminants and increase MTBC. Our expertise in deep silicon etching has been recognized within the MEMS arena for decades since bringing the first commercial DRIE system to market in 1995. This DRIE technology has been successfully transferred to 3D-IC packaging for through silicon via (TSV) etching, and into plasma dicing of standard and taped wafers up to 300mm. Other processes include low temperature PECVD for dielectric deposition onto standard, bonded or fan-out wafers, and HF/XeF2 release etch for MEMS release or wafer level packaging applications. Recent acquisitions have expanded our portfolio to include Molecular Vapor Deposition (MVD®) which is used for anti-stiction films for MEMS and anti-oxidation & -corrosion layers for packaging applications. Finally, from the PCB division, we can also offer inkjet products for 3D printing of underfill dams and isolation layers, and laser systems for through-mold via formation.

Dow Electronic Materials

As a global supplier of advanced specialty materials, Dow Electronic Materials provides innovative solutions for electronic and semiconductor industries across several segments, including advanced packaging. One example of how Dow Electronic Materials is focusing innovation on addressing key technical challenges in the advanced semiconductor packaging market is with the introduction of SOLDERON™ BP TS 6000 Tin-Silver. Since its introduction to the market, it has rapidly become the leading lead-free solder chemistry for advanced packaging applications. Tin-silver is essential for reliably capping copper pillars, particularly as higher I/O counts and tighter pitches become the norm. No other commercially available solder chemistry has met this tin-silver performance and reliability from a single formulation. SOLDERON BP Tin-Silver is proven in HVM with excellent process flexibility, especially with its wide plating speed range and the tunable nature of silver composition. Dow Electronics Materials has built a strong portfolio of advanced materials providing innovative technologies for metallization, dielectrics, lithography and bonding applications as well as integrated solutions addressing current industry requirements and next generation packages.