By Julia Woertink, VP of R&D of Semiconductor Technologies at Qnity Electronics
For decades, semiconductor progress followed a simple formula: shrink the transistor, fit more on a chip, and deliver more performance at lower cost. That formula still works, but it no longer works alone. Each new node in both logic and memory is harder and costlier to reach, and AI workloads demand far more compute than shrinking can deliver on its own.
So the industry is building up as well as down, stacking logic, high-bandwidth memory (HBM), and other components into tightly integrated 2.5D and 3D systems. The path to performance has moved from “shrink” to “shrink and stack.” The result is that advanced packaging has become one of the tightest constraints on AI hardware, with demand for leading-edge 2.5D packaging continuing to test available capacity, even as the industry expands supply.
Most of that story is being told through foundries, OSATs, and chipmakers. Less attention goes to the metals, dielectrics, and substrates that make these packages possible, and to the suppliers who determine whether next-generation architectures can scale.
AI’s New Packaging Requirements
Next-generation AI accelerators are outgrowing today’s packaging formats. Each generation pairs more compute dies with more HBM stacks, pushing interposer sizes toward the practical limits of a round 300 mm wafer, where large rectangular packages leave wasted area at the edges.
The industry is moving towards two emerging approaches. Glass-core substrates promise exceptional flatness, a tunable coefficient of thermal expansion (CTE), and finer wiring than organic laminates. Panel-level packaging (PLP) moves processing from round wafers to large rectangular panels, enabling greater manufacturing area efficiency and potentially supporting larger, more complex chip packages.
Both depend on materials performing in ways they never have before. That makes materials suppliers critical strategic partners in deciding which architectures move forward, when, and how.
From “Shrink” to “Shrink and Stack”: Why Materials Selection Has Changed
Shrinking was always a materials story. EUV lithography required new photoresists, and high-k dielectrics and metal gates were needed to control leakage as transistors shrank.
Stacking raises the stakes. Vertically integrating dies unlocks substantial gains in performance, bandwidth, and power efficiency, but it means solving several problems at once: heat trapped between layers, through-silicon via (TSV) alignment, hybrid bonding, mismatched thermal expansion, mechanical stress, and power delivery. Addressing these challenges requires precise engineering and, most critically, the selection of materials with the right properties at every interface. Each added layer brings more process steps, greater material intensity, and tougher demands on power, heat, signal integrity, and long-term reliability. That is why materials selection belongs at the start of development, not the end. Glass-core and panel-level formats will only intensify those demands, so the materials decisions made today will help determine which designs can scale tomorrow.
Where Glass-Core and Panel-Level Packaging Still Face Hurdles
Both approaches still face real manufacturing, materials, and integration challenges ahead of high-volume production.
Glass-core substrates face three. First, glass is brittle; without the forgiveness of organic laminates, it is prone to microcracking during handling, drilling, and dicing, which drives yield loss. Second, copper does not bond readily to glass, making reliable adhesion difficult. Third, through-glass vias (TGVs), the microscopic holes that must be completely filled with copper to form reliable connections, are vulnerable to voids and uneven deposition.
Panel-level packaging faces its own challenges in warpage and qualification. AI packages combine silicon, copper, dielectrics, and molding compounds that expand and contract at different rates as temperatures change. Across a large panel, those mismatches add up to warpage that disrupts lithography, die placement, and bonding. And because panel tools and processes are newer than their wafer counterparts, every material must be requalified at panel scale.
Materials advances are closing these gaps: adhesion-promoting layers and seed processes that let copper bond to glass, plating chemistries that deliver fast and void-free TGV fill, low-stress dielectric films that hold panels flat, and thermal solutions that move heat out of dense stacks.
Packaging Constraints Are as Much a Materials Story as a Manufacturing One
Limited packaging capacity is only part of the reason accelerator and GPU supply has struggled to keep pace with AI demand. Specialized materials are an equally limiting factor. Larger, more complex packages depend on materials that meet stringent specifications, and only a small pool of suppliers can meet them. When any one of those materials runs short, production can stall, as recent tightness in low-CTE T-glass for substrates has shown.
Building resilience means diversifying materials sources and working with partners whose roadmaps align with where packaging is headed and who can manufacture close to customers in key semiconductor regions. Technical performance makes a material viable; reliable availability makes production possible. Supply chain resilience starts with giving materials partners the same attention in strategic discussions as in technical ones.
What to Ask Your Materials Partner Before Committing to a New Platform
Before committing to a next-generation substrate platform, design and packaging teams should ask their materials partners four questions.
Has this material been qualified at the dimensions and volumes we’re targeting? Lab-scale qualification does not guarantee readiness for high-volume production on large panels. Asking early keeps cost and schedule from becoming late-stage surprises.
Can you supply at scale, from more than one site? A material available in limited quantities from a single source is a bottleneck waiting to happen. Resilient supply chains have multiple qualified options, ideally produced close to where packages are built.
How does your roadmap align with where packaging is heading? Suppliers whose priorities lag glass-core and panel-level timelines will slow programs down. The strongest partners invest ahead of the industry.
How will you support us when qualification doesn’t go as planned? This answer separates a vendor from a strategic partner. A vendor fills orders. A partner anticipates where the technology is going, flags problems before they become failures, and stays invested in the outcome.
Treating Materials as a Long-Term Business Strategy
Solving the packaging bottleneck will take more than new architectures and added capacity. It will take a deliberate materials strategy, one that treats materials choices as long-term business and engineering decisions. Teams that bring materials partners in early will qualify faster, scale more reliably, and avoid costly redesigns. As stacks grow taller and packages grow larger, materials innovation, not procurement, will be one of the defining drivers of AI hardware.
