3D ASIP 2017

3D ASIP 2017

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Date/Time
Date(s) - 12/05/2017 - 12/07/2017
All Day

Location
San Francisco Airport Marriott

Category(ies)


Now in its 14th year, 3D ASIP 2017 has been re-branded from 3D Architectures for Semiconductor Integration and Packaging to 3D Architectures for Heterogeneous Integration and Packaging, reflecting the recent focus of the semiconductor industry away from Moore’s Law towards heterogeneous integration.

This conference presents a broad, yet thorough perspective on the techno-market opportunities and challenges offered by building devices and systems in the vertical dimension, and provides participants the unique opportunity to gain the latest technology and market insights on 3D integration and packaging efforts, and technology and industry trends impacting this dynamic arena.

Conference leaders Dr. Phil Garrou – Microelectronic Consultants of NC, Dr. Mitsu Koyanagi – Tohoku University, and Dr. Mark Scannell – CEA Leti, working with the conference session chairs have hand picked 30 presentations and 4 keynotes covering 2.5/3D enabled applications; high-density fan-out; image sensor technology; advanced assembly technology; µbumping and copper pillar technology and equipment and materials..

These presentations will include:

  • TSMC updating us on InFO technology
  • Cisco discussing HBM test challenges
  •  Intel updating us on EMIB technology
  • Besi sharing thin die handling techniques
  • Sony detailing their advanced CMOS Image sensor stacks
  • Olympus sharing their CMOS Image sensor stacking technology
  • Micross detailing 10um pitch µbump bonding

In addition, this conference will include the first public presentations on the new DARPA groundbreaking program CHIPS, including a keynote by DARPA PM Dan Green and presentations by Northrup Grumman, Lockheed Martin, Boeing, Intel and U Michigan.

For those needing refresher courses, the following three tutorial courses are offered just prior to the start of the conference program:

  • The Evolution of High-Density Packaging”, Dr. Phil Garrou – Microelectronic Consultants of NC
  • “Fan out Packaging – Evolution and Complexity”, Dr. John Hunt – ASE
  • “Intro to Solder Flip Chip with Emphasis on Copper Pillar” Dr. Mark Gerber – ASE

Details are available here.