Mentor xSI and Calibre 3DSTACK
2019 Edition. In
During the development of a complex FinFET-class ASIC, there were several modifications to netlist names and package connectivity to maintain compatibility with a legacy product. These events created the opportunity for inconsistent data.
The use of XSI and 3DSTACK to do a system-level LVS allowed us to detect out-of-sync connectivity between the design intent and the design implementation, even though the individual design systems were passing LVS/DRC. The same LVS allowed us to detect and prevent potential opens/shorts that could have occurred between the package and the PCB, avoiding a costly and time-consuming re-spin.