• Solutions for 3D IC test are ready today, but they will be more ready tomorrow. At the 2015 ISTFA, I presented a tutorial titled “What is New in 3D, Digital Testing?” and I’ll summarize the main points here. I con […]

  • [caption id="attachment_9145" align="alignright" width="300"]IEEE P1838 3D test working group[/caption]

    Accelerating the adoption of interposer and 3D designs depends on several advances across the design and manufacturing ecosystem. Standards are a part of the ecosystem.

    Now, stay with me. I know standards put some people to sleep, but I won’t be going into any gory details, just talking about the motivations and status of some key standards relating to silicon test.

    First, there is an update to the well-known JTAG test access standard, IEEE 1149.1-2013. Next, we have a brand new standard called IJTAG, or IEEE 1687-2014, which also offers an IP access methodology. I’ve heard someone say that the new 1149.1-2013 is all you need, but I’ll go on the record to say IJTAG is much more powerful for pattern and IP reuse, and that it incorporates IEEE 1149.1-x and the design-for-test standard IEEE 1500.

    The next test standards in the pipeline are specifically designed for 3D test: IEEE P1838 will standardize 3D interoperability between multiple logic die from different vendors; and JEDEC, or FEFSD229, define how to interface the topmost logic die to memories for wide-IO memory test.

    The P1838 standard aims to reuse IEEE 1500, 1149.1-x, and maybe IEEE 1687. Any good test strategy for 3D first requires great 2D test; it will be more important to make sure your die are good before stacking them. The technology for great die test is available in the form of embedded compression and logic BIST. Once you stack logic-on-logic, the test methodologies are not mature. All EDA companies are working on it, but we need IEEE P1838 to define a standard architecture to support heterogeneous die from multiple vendors.

    At ITC this year, the P1838 working group delivered a status report. They are in the thick of hammering out details. The focus is on generic test access to and between dies in a multi-die stack with TSV interconnects (except for memory die), and the standard applies to individual die. So, each die in a stack will need to be IEEE P1838 compliant, which means the use of wrapper circuitry per die. It does not include how to connect to and test a memory on top of a P1838-compliant stack. It will define the number, name, type and function of test port IOs, the clock-cycle accurate test operation protocol, and test hardware and protocol description language. However, all this is still not enough to get P1838 compliant dies to plug-and-play in a stack. You need more parameters to properly align TSVs, for example. Regardless, 3D test will take a great step forward when P1838 is ready. If you are involved with 3D design and test, I suggest you learn more about it and keep track of their progress. ~ M.K.

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