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John Lau wrote a new post, Perspectives on the Cost of Fan-out Wafer Level Packaging vs. Flip Chip Packaging 2 months, 1 week ago
Recently, I read a paper published in the 2017 IMAPS Device Packaging Conference proceedings, titled “Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging,” written by Amy Lujan, of Savansys. […]
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John Lau wrote a new post, MCM, SiP, SoC, and Heterogeneous Integration Defined and Explained 1 year, 2 months ago
Multichip module (MCM), system-in-package (SiP), system-on-chip (SoC), and heterogeneous integration are all important semiconductor packaging technologies. They deserve to have, at the very least, a book w […]
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John Lau wrote a new post, Warpage Issues in Fan-Out Wafer Level Packaging 1 year, 3 months ago
As you all know, warpage is a critical issue for fan-out wafer/panel level packaging. Many people like to talk about it, however, most of them don’t know what they are talking about. Let’s use the chips first […]
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John Lau wrote a new post, Are Glass Substrates the Next Option for Fan-out Packaging? 1 year, 5 months ago
As you all may know, in most fan-out wafer level packages (FOWLP) such as embedded wafer level ball grid array (eWLB) by Infineon and STATS ChipPAC, and TSMC’s integrated fan out (InFO), the chip(s) are embedded […]
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