• In our last article, we talked about a project we participated in to test the feasibility of an assembly design kit (ADK) for package design verification. This time, we’d like to delve a little more into the r […]

  • ThumbnailUnlike the traditional system-on-chip (SoC) design process, which has fully qualified verification methods embodied in the form of process design kits (PDKs), chip design companies and assembly houses have no […]

  • Historically, we all took Moore’s Law for granted. With each new node, we could expect to see faster-performing devices, smaller design footprints and, ultimately, lower design costs. Nowadays these benefits are not clearly achievable for all designers. At the latest advanced technology nodes, we may be able to see faster devices through the miracles of finFET technologies, but do we really get the smaller form-factors? In many cases, the additional rules required for such technologies prevent it. At the same time, the sheer increase in the number of additional masks, coupled with the increased mask costs, makes the cost benefits questionable. For this reason, the industry has begun to explore alternative design practices in an effort to regain some of these benefits. Collectively, these approaches are often referred to as “More than Moore” technologies.

    We know that 3D IC design methodologies are one such technology, the goal being to partition what would otherwise be a physically large area into smaller pieces that can be stacked, resulting in smaller form factors, allowing us to pack more functionality into tablets and other hand-held devices. Theoretically, targeting less-expensive process technologies for all but the most critical components can also result in a cost savings, though that is still debatable. But, aside from some novel design concepts (such as the memory cube), typically you will not see a performance advantage. In fact, because stacking requires the introduction of through silicon vias (TSVs) to pass the signal between dies, we may get a performance degradation, along with a power penalty and countless other concerns (compared to a single chip solution).

    [caption id="attachment_9347" align="alignleft" width="300"]Silicon photonics An IBM silicon nanophotonics chip combining optical and electrical circuits on different layers. (Courtesy of IBM)[/caption]

    Another of the More than Moore technologies is silicon photonics. Photonic design is the art of moving and transforming signals in the form of photons, allowing the message to literally travel at the speed of light, and bringing the promise of significant performance gains. Because light signals can pass through each other essentially unimpeded, this also brings the theoretical ability to eliminate the need for vias, dramatically reducing the power required to pass said signal.

    As luck would have it, silicon surrounded by silicon-oxide makes an almost ideal waveguide material, meaning the optical signals can traverse with very little degradation. This has raised the possibility that photonics can be designed and manufactured using the same fabs already in place for traditional IC design. But, of course, there is always a catch. The issue for photonics design is that it really is purely passive. If you want to change an optical signal, you must induce that change using either heat or a magnetic field (or both) in the vicinity of the waveguide carrying the signal. Of course, using basic electronics, we already know how to design such controls, so the concept of photonic-electronic co-design sprung up.

    So, all we have to do is create a design with some photonics components and some electronics components and we’re done; we simply pass timing-critical data as optical photons and use tried and tested electronics elsewhere, right? Well, maybe not. Depending on the complexity of your electrical configurations, you may need to target those expensive CMOS processes again. Unlike the CMOS transistor, however, there is little benefit in porting a silicon photonic waveguide to an advanced node. That is because the optical behavior for such components is set by the total length and width of the wave guide, along with some other concerns, like bend structures or how close it is to other components. The widths for waveguides in silicon are very large (100-200nm) compared to today’s CMOS devices. So, even if you go to a new process node, the photonics section stays the same size. Sure, you might get a little better lithographic integrity through the printing stages, but is it worth it?

    Here is where things may get interesting. If we combine silicon photonic processing with 2.5D processing, then perhaps we can partition the optical components to a less expensive process, such as those typically targeted for interposer use (like, say 90nm), while targeting those more critical electrical components to a die on a more advanced process node, maybe 28nm. Then we may be able to bring together the best of both worlds! This is, in fact, where a lot of photonics research is currently targeted.

    Unfortunately, we’re still not there yet. There are lots of questions that still remain to be answered. For example, if we were to create photonics components on a 2.5D interposer, connected electrically to an advanced node die for electric components, then we’re back to relying on TSVs. How much benefit in terms of performance and power will be lost in this trade-off? When we stack the dies, loaded with TSVs, we’ll invariably generate heat and stress. What impact will this have on the photonics components? The photonics will require a laser source, but because we’ve yet to produce a usable silicon laser in standard CMOS process, it will need to sit off-die. What impact will this have on the form-factor? What impact will the heat generated by the laser have on the near-by electronic components?

    As you can see, we still have a long way to go. As is usually the case, in uncovering the answers to these questions, we will learn more, allowing us to open up yet further design practices. So while we’re not there yet, there still seems to be a bright future on the horizon. ~ J. Ferguson

    • “because stacking requires the introduction of through silicon vias (TSVs) to pass the signal between dies, we may get a performance degradation, along with a power penalty” – really?
      In our experience at Tezzaron, stacked chips with TSV have higher performance and lower power requirements. Our very first 3D-IC chips (in 2004) showed a huge performance improvement over a 2D solution; when throttled back to match the speed of the 2D solution, they ran at 1/10 the power.
      Just last year, Georgia Tech and the U of Michigan demonstrated some amazing high-performance and low-power 3D work as well.

      • Thanks Gretchen! I think no doubt that you can accomplish higher performance and lower power, especially versus 2D implementation with lots of vias and metal layers. I guess my question is more about do we still see the same kind of power and performance advantage as compared to photonic processing, not just traditional IC. At somepoint we need to convert between photonic and electronic signals. In the process of doing so, whether we’re pushing the electronic signal through a TSV or standard vias, how much advantage from the photonic speed is now lost? I think like most things it will come down to clever and innovative design techniques to minimize those impacts.

    • Love to see this dialogue between the process engineers and design engineers. This is EXACTLY what the industry needs to move this forward. Please keep it going folks!

  • As an integral part of the established integrated circuit (IC) supply chain, Outsourced Assembly and Test (OSAT) companies offer IC packaging services on the open market, independent of the chip manufacturer or foundry. OSATs are a subset of the total worldwide IC packaging market, since some IC package assembly is still performed in-house at integrated semiconductor manufacturers (ISM). However, both fabless design houses and ISMs alike use the services of OSATs. Companies with their own packaging facilities use OSAT companies for work beyond the capacity of their own plants, and also for specialty packaging. Unfortunately, OSAT companies are usually the “tail end of the whip”—they often take the brunt of business swings in the semiconductor market. When the economy is down, semiconductor manufacturers will fill up their own packaging plants before contracting the work out to the OSATs, who can then be left with less work. Conversely, when the market is up, the OSATs’ plants are filled to overflowing. The result is that swings in the semiconductor market can have an accentuated effect on OSATs.

    To achieve a more stable and profitable business model, many OSATs are investing in cutting-edge packaging technologies, allowing them to consume a larger percentage of the overall worldwide IC packaging market over time. One of the more interesting opportunities for OSATs is interposer and 3D packaging. While the value and benefits from advanced interposer and 3D die packaging have been validated in a number of established designs, the adoption of these design techniques is still relatively narrow and limited. One of the reasons these techniques have not yet reached mainstream is the lack of vetted and qualified process design kits (PDKs) for interposer and 3D designs. In the foundry world, PDKs help speed adoption by providing designers with the setup configuration and data files required by their design tools and the foundry process. They also lower risks, because a foundry will stand behind its delivered PDKs with support for and guidance on their use.

    However, by definition, interposer and 3D design assemblies contain multiple die in a single package, and these die can each be based on different process technologies, and may come from different foundries. Currently, design teams working with interposer and 3D products waste valuable time establishing their own design methodologies and tool sets, often in a vacuum, missing out on the experiences and best known practices of others in the supply chain. To make interposer and 3D integration a more efficient and less risky process, we need a assembly-level PDKs to augment existing foundry PDKs. Such a PDK would include, for example, information on how to place the dies, rules for routing between dies, DRC style checks for die-to-die alignment, rules for connection verification, materials and thickness information for use in parasitic extraction, and thermal analysis information.

    Unfortunately, this is not an easy task. Adding to the complexity, there are many different approaches used to implement multi-die packaging: interposers, multiple die-to-die stacking approaches, package-level routing between die, and the newly-announced embedded silicon bridge technologies. With all the different approaches and suppliers in the design flow, where would such a PDK come from, and how can it be validated?

    This could be a great opportunity for OSATs and packaging houses to incorporate best practices into qualified PDK’s for their offerings, providing a foundry-like model to their customers to achieve more reliable results. Customers need an integration platform that can assemble and optimize complex (multiple die and interposer based) packages, and tools that are flexible enough to adapt to new packaging technologies as they emerge. Specific tools and flows will depend on the mode of packaging their customer’s design environments. Delivering this capability requires the OSATs to step up to a new level of sophistication, similar to what foundries have done to support their customers. They need to supply more definitive characterization of their processes and offerings and compile this information into a PDK-like format.

    Today, some suppliers are responding to customer demand, but in general, OSATs have not yet embraced this approach as a competitive advantage. To complement and assist the OSATs, EDA vendors need to collaborate with them to determine how their process characterizations can be incorporated into design tools that support the customer. Although the package PDKs could potentially come from the EDA vendors, that would lock customers into a single tool solution, so it would best for the OSATs to provide “vendor neutral” PDKs for their processes. Package-level PDKs would not replace foundry (die-level) PDKs, but rather supplement them with the additional information needed for assembly.

    In addition to the PDKs themselves, OSATs could also help customers by providing “how to” information to help them take best advantage of the services they offer. For example, the challenge in testing has more to do with using the right methodologies during design to ensure that a multi-chip product can be tested thoroughly and efficiently. This type of support might be categorized as best practices, and would be similar to the reference flows that foundries qualify for their customers. In fact, qualified reference flows for all aspects of the OSAT’s services would be a boon to many IC designers, especially ones in emerging economies, or those moving up to more advanced technology nodes, or to specialty processes like MEMS or silicon photonics.

    These ideas have already moved beyond speculation, as Mentor Graphics and others have started working with OSATs to define commercial assembly PDKs and tools that can use them to provided advanced design capability for 3D-IC designs. Nevertheless, there is still a significant amount of work to be done, so consider this a call to action for the industry and supporting industrial and academic research institutions to work on the needed technologies. For example, we need better models at the package level for mechanical and electrical stress effects, electro-migration, electrical breakdown, thermal behavior, signal integrity and coupling, parasitic effects and other phenomena. We also need ways to certify PDKs and reference flows, and to ensure they are interoperable across suppliers. A lot of this can be modeled on the successful approaches pioneered in the foundry industry—it’s more a matter of vision and initiative. We’re convinced this is the most flexible and efficient approach, so the market should reward first movers who grab the ring. ~ J. F.

    • Thanks Surya, looking forward to working with you further along these lines in the coming year!

    • Thanks Herb,

      Your insights are always appreciated. Looking forward to working with you further in this area through 2015.


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