• The adoption of 3D ICs allowed the elimination of the “Memory Wall” using a new memory architecture and through silicon via (TSV) technology. While individual ICs became faster with each process node, the com […]

  • E. Jan Vardaman, TechSearch InternationalIn an era where people expect instant everything, the development of the market for 3D ICs with TSVs has not met many expectations. But for those who really understand how long it takes to bring a new technology to maturity, it should be no surprise. It has taken memory companies more than 10 years of development to bring out commercial 3D IC products with TSVs. Other than die stacking for image sensors, these represent the first volume commercial product introduction. Just as with many technologies, the high-performance applications that can afford the price of early adoption are the first markets for stacked memory.

    At TechSearch International, we expect 2015 to be the year of the memory stack. It will also be the year of engineering progress. In order for 3D ICs to be designed into other new architectures, co-design at the system level—from IC to package to board — is essential. We expect new introductions in the EDA tool space, and hopefully a greater understanding of how to design in 3D instead of 2D across a broader range of applications. We also expect to see continued developments in manufacturing processes that will enable cost reductions by improving yield and throughput. This includes continued development of materials for use in the bond/debond process. Thermal challenges still remain for applications that involve memory and logic stacking or logic and logic stacking, but we are hopeful for progress in new architectures that will lead to future solutions.

    Many of the 2.5D or interposer solutions depend on the availability of stacked memory, and with the delivery of memory stacks, these applications are expected to see some expansion. However, it is important to remember that many of the first applications in this space are also high-performance applications and therefore are not super high volumes. While there are investigations for the use of interposers for mobile applications, cost and infrastructure readiness relative to other alternatives is a deciding factor in adoption. A number of companies are investigating the potential for glass interposers. Significant progress has been made in the fabrication of fine lines and spaces (2 to 5µm) and small diameter vias (<25µm). While there are many applications for glass, the adoption of interposers for high volume applications such as the mobile device space requires a strong supplier base, experienced assembly partnerships, and plenty of reliability data.

    We may have been living in the years of PowerPoint engineering in the past, but 2015 will be remembered as the year of really exciting engineering work. ~ E. Jan Vardaman


  • I attended the 3D IC Technology Forum at SEMICON Taiwan 2014, where many of the discussions focused on the latest memory announcements in 3D ICs from Micron, SK Hynix, Samsung, and Tezzaron. While the world still waits for the introduction of a Wide I/O mobile DRAM and logic part, memory is clearly moving into production.

    The focus of Taiwanese OSATs in the 2.5D space, such as SPIL and ASE, is to work with interposer suppliers to provide processing after the vias are fabricated and provide assembly of the die on the interposers. SPIL described its focus on enabling 2.5D assembly and working with multiple foundry partners. Research in overcoming challenges such as substrate warpage was discussed. ASE described its readiness for middle-end-of-line (MEOL) and 28nm silicon node top-die assembly. Reliability data for the 8mm x 8mm ASIC mount on an interposer was presented.

    The ability to partition a design so that only the critical features are fabricated in the newest (most expensive) technology node has clear cost advantages. This includes considerations for mask cost, defect density, and yield. Inotera Memories described its interposer offering and exclusive partnership design with ASE. The relationship started two years ago and is being promoted as a fast cycle time potential for silicon interposer design and assembly. Inotera repots that interposers up to 24mm x 36mm can be fabricated with 40µm micro-bump pitch and RDL on both sides of the interposer.

    Mentor Graphics provided insight into integrated design with 2.5D and 3D ICs. Optimal Plus highlighted leveraging of smart screening and smart pairing to reduce cost in 2.5D and 3D IC, emphasizing the importance having a good die stack. IBM and Senju discussed the injection molded solder technology for solder bumping on wafer and laminates—pointing out the need for fine pitch bumps in the future.

    Presentations from equipment vendors SUSS MicroTec and EV Group highlighted the advances in equipment and the plethora of materials that have emerged for the bond/debond process—a step in the 3D IC process that requires yield improvement to lower cost.

    IMEC’s presentation focused on advancements researchers have made to solve issues that slow adoption of 3D ICs. IMEC’s process of record (POR) is 5µm vias with a depth of 50µm and research is focused on even smaller vias of 3µm or even 2µm diameters. Challenges in scaling micro pitch down to 20µm were highlighted. IMEC described the importance of a good CMP that produces a flat surface in the hybrid bond process.

    The panel discussion included the importance of wafer edge processing, the potential for permanent bond as an alternative to temporary bonding, and thermal management needs. Thermal design tools were highlighted as critical to the success of future implementations. ~ Jan Vardaman

  • ThumbnailA recent IEEC and IEEE CPMT workshop held on October 16, 2013 at Binghamton University in New York examined the status of 2.5D and 3D ICs for high performance systems. There is no question that 3D ICs with through […]

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