• In contrast to some of the gloomier predictions of the analysts, we think 2016 will be a growth year for our business. In packaging, we see a number of development projects moving into production this year, and a […]

  • David_Butler-cropIn June 2014, SPTS co-produced a webinar with Ron Huemoeller of Amkor, titled “2.5D and 3D Packaging at the Tipping Point.” We forecasted that significant product announcements would be made over the next 18 months and we were right; sk Hynix, Samsung and Micron all announced readiness for their 3D stacked memory packages, and at the end of the year, AMD started risk production on a high bandwidth 2.5D interposer package, featuring a graphic chip next to four High Bandwidth Memory (HBM) stacks from sk Hynix. These products offer 3 to 4 times higher bandwidth without exceeding power budgets, and will ramp through 2015. This is a watershed moment for those of us who have invested heavily in 3D technology; once production starts, costs will drop and others will follow into HVM.

    2014 also saw TSV technology expand into other applications; multiple image sensor companies started 300mm 3D wafer level packaging (3D WLP) lines, and MEMS devices began to transition away from wire bonding into via last TSV to stay on their package size reduction roadmaps. All this confirms what SPTS and the fabs have been saying for some time – TSV technology yields well and is production ready. 2015 will be the year our 3D etch, CVD and PVD technology moves into high volume manufacturing.

    However, the applications that have embraced (interposer) and 3D are a small subset of the market, and use them because their performance or form factor objectives cannot be achieved by traditional packaging. The goal now is to expand high performance packaging into volume markets, and for that, costs have to fall. 2014 saw an emerging trend of embedding die on mold based substrates, avoiding costly through silicon vias. TSMC, Amkor, SPIL plus others have made product announcements on these high-density wafer-level fan-out (WLFO) formats, claiming significant cost reductions over TSV-containing packages. This will be a large area of focus for SPTS in 2015; embedded wafer-level ball grid array (eWLB), the first WLFO platform, was developed by Infineon on our PVD systems and we have introduced a number of features designed to meet the challenges of mold substrates such as contamination & wafer bow. We continue to refine those benefits as packaging companies develop their own WLFO concepts. ~ D. B.

  • In 2013, SPTS equipment sales into the advanced packaging market grew by 75%.  Some of this was due to a resurgence in 3D wafer level packaging (3D WLP); the first-generation 3D that started with CMOS image sensors in the middle of the last decade. This year’s growth was predominantly due to the demand for fingerprint sensors first seen in the iPhone 5S;  next to be used in competing phones and other security-sensitive devices. That, together with more cameras in automotive means that 3D WLP will continue to be the largest volume TSV application in the near term.

    2013 also saw the start of via-last TSV production on 200mm for MEMS and other small package devices. OSATS took completed MEMS devices from the IDM and etched TSV’s from the backside of the wafer. These packaged parts are yielding at levels equal or better than their wire bonded equivalent but provides the added benefit of smaller footprint. This progress implies that device manufacturers and packaging partners have worked out at least some of the long-standing concerns over shared IP and die testing – a significant step as we approach the era of 3D packaging of multiple die.

    At the ECTC conference in May 2013, we presented work on dielectric stack engineering for wafer backside applications.  Low level production has started on 2.5D interposers, but one technical challenge is warpage of large area Si interposers. During the bump reflow step the die can distort by some microns meaning failed bump connections from die to substrate.  To address this problem, SPTS and our partners are developing stress compensation dielectric stacks on the die backside, using our low temperature TEOS oxide and nitride processes.

    At the 3D Architecture for Semiconductor Integration and Packaging (3DASIP) conference in December, Eric Beyne of IMEC said that the backside processing steps were more demanding than the TSV formation on the device side. Eric believes TTV needs to be controlled to <2µm, and the vias revealed to 2 to 3µm.  If that can be maintained, he said, the need for costly CMP can be avoided.  SPTS has been leading the way in backside cost control through our unique ReVia™ endpoint system that detects the via tips as they emerge from the Si surface.   Simple timed etching cannot provide the level of control needed.  ReVia automatically compensates for any variation in Si overburden, giving consistent via heights wafer to wafer.

    In 2014, we will see 3D WLP leaders move to 300mm wafers, and an increase in low I/O devices packaged with via-last TSV.  We will take a big step towards 3D high volume manufacturing (HVM) with the introduction of the stacked memory cubes for high bandwidth applications.  Beyond that, technical and economic challenges need to be solved in order to make TSV the industry standard packaging method.  At SEMICON Europa 2013, SPTS COO Kevin Crofton called for deeper relationships between the fabs and equipment makers. By adopting a more open working model with equipment vendors and leveraging their knowledge, we believe that the time to HVM can be reduced. ~ D.B.

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