Guest bloggers from across the supply chain and from various market segments contribute to provide insight on the implications of 3D integration technologies. Industry experts who have something to say are invited to participate.


Embedded Die: from Incubation to High Volume Production

The embedded-die-in-substrate platform has its own history and adoption scheme compared to other advanced packaging platforms, explains Yole Développement (Yole). Indeed while the first significant volume of embedded die in integrated circuit (IC) package substrates came from direct current (DC) converters in smartphones, penetration in other market segments of interest to embedded die such as au... »

iPhone 7: Apple Charts a Strategic Course by Selecting TSMC’s inFO Platform

Each year, Apple integrates more and more innovative technologies in its iPhone products. This year, with the new iPhone 7 and its A10 processor, the leading company is the first organization to bring out package-on-package (PoP) wafer-level packaging (WLP) at the consumer scale. Apple underwent a strategic change by selecting TSMC’s new integrated fan-out PoP (inFO-PoP) technology for its new A... »


3D TSVs are essential for Heterogeneous Integration, HPC and High-end Memory

This year again, both market segments, high end, and low end, are the main targets of through silicon via (TSV) technology providers. In its latest advanced packaging technology and market analysis entitled 3DIC and 2.5D TSV Interconnect for Advanced Packaging: 2016 Business Update report, Yole Développement (Yole) announces, high volume production started: 3D TSV is a reality, especially in the ... »

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Will The Lifespan of CMOS Integrated Circuits End?

There is fierce competition for scaling foundry logic technologies. However, according to the 2015 International Roadmap for Semiconductors (ITRS), logic transistor scaling will stop at 10nm and it will no longer be economically desirable for companies to continue traditional transistor miniaturization in microprocessors1. How will this impact the lifespan of CMOS integrated circuits? (Figure 1)... »


System Plus Consulting confirms: Apple A10 processor uses TSMC’s inFO technology

System Plus Consulting announces the release in the next few weeks of a complete report on TSMC’s Integrated Fan-Out (inFO) technology used for Apple’s A10® processor packaging. And few results are already available. Indeed System Plus Consulting’s experts propose you to discover a previous of the first conclusions. Featured in the latest Apple iPhone 7®, the Apple A10 processor has high... »

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Quantum Mechanical Advantage: A Revolution through Evolution for Storage Class Memory

I was again struck by the same epiphany as last year as I escaped the Californian sun to reach the air-conditioned Flash Memory Summit (FMS). The major part of the solid state storage industry depends on NAND Flash. All NAND Flash, whether it be 2-D or 3-D, floating gate or charge trap, depends on a quantum mechanical effect called tunneling or barrier penetration. This effect, discovered in the l... »


The Growth and Emergence of New Dicing Technologies

Driven by rising demand for thinner wafers and stronger die, dicing technologies are evolving. “Reaching more than US$100 million in 2015, the dicing equipment market will double by 2020-2021”, announces Yole Développement (Yole) (Source: Thin Wafer Processing & Dicing Equipment Market report, Yole Développement, May 2016). Yet at the same time, thin wafers are creating new challenges of... »

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SEMI 2020: Transforming for the New Supply Chain

2015 will be remembered mostly for the ‘wild ride’ that fundamentally changed the industry.  An unprecedented wave of M&A activity swept across the electronics supply chain with scores of transactions and with notable multi-billion dollar companies being absorbed.  As a result, in 2016, we are working within a significantly reshaped supply chain. To support this, we have launched the SEM... »

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Convergence on the “Big Five”: Focus on Wafer-based Advanced SiP

In the fourth installment of the series “Convergence on the Big Five,” we compared conventional SiP with advanced system-in-package (SiP), which is focused on laminate-based approaches, and is available and in production today. Advanced SiP packaging has been a game changer in addressing system-level integration and providing the lowest form factor at cost and performance points that address m... »

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Convergence on the “Big Five”: Focus on Laminate-based Advanced SiP

Part four in a five-part series While many industry experts have long predicted the demise of Moore’s law, it’s only in the past few months that it seems we have exhausted current CMOS scaling methods. While it’s likely that scaling approaches will resume in the future as new materials, processes, and tools are developed, the reality is that these solutions are still in the early stages of d... »

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