Through-silicon vias (TSVs) have been firmly established as a method of interconnect that enables high bandwidth and low latency between dies at extremely low power dissipation. Used for years in microelectromechanical systems (MEMS), compound semiconductors, and image sensors, TSVs are now also in mainstream production for 2.5D interposer technologies, and for stacking die to create high-bandwidt... »
The people have spoken! The results of last week’s poll are in, and it looks like the majority of those who participated think we should keep it simple. When it comes to heterogeneous integration nomenclature for package architectures, it should be 2D or 3D. The Back Story The term “2.5D” has been a topic of debate in the advanced packaging world ever since it was first added to the industry... »
Well, that was interesting. SEMICON West 2018 just wrapped up, and I’m not quite sure what just happened. This year’s event was… for lack of a better word… different. All I could think of as I looked around the Moscone Center upon arrival was “ready or not, SEMICON West 2018 is here, emphasis on ‘or not.’” While I generally endeavor to paint a rosy picture, I have to remember that ... »
Ok folks. It’s that time of year again. SEMICON West 2018 is upon us. By the time you read this – IF you get the time to read this – it’s almost curtain time. Everything that needs to be prepped is done, and if it’s not, it’s too bad, because the show will go on! It seems like every year, there’s more and more content to choose from. And you must choose because it’s pretty much... »
The Heterogenous Integration Roadmap Committee wants to create a new nomenclature that does away with 2.5D. Instead, the industry will refer to 2D, 2D enhanced (formerly 2.5D) and 3D architectures. 2D enhanced will be further categorized as 2DS (silicon substrate) or 2DO (organic substrate). We want to know your opinion. After you vote, please stop by booth 2330 in the South Hall during SEMICON W... »
One topic that has been under hot debate in the semiconductor advanced packaging sector for the past few years is fan-out panel-level packaging (FOPLP). In theory, the concept of taking fan-out from a 300-mm reconstituted wafer to a large panel format as a way to lower costs seems simple, and even the logical step. It’s not. Skeptics, many burned by the same low-cost advantage argument for inv... »
These days, the first thing that comes to mind when someone mentions fan-out (FO) technology is Apple’s A10 processor built on TSMCs integrated fan-out (InFO) technology. It’s the superstar application that put FO on the map and into high volume manufacturing. However, equally important to remember are the numerous low-density FO workhorses supporting other mobile applications, as well as mark... »
For the past few years, the ECTC committee has provided 3D InCites with a table outside the session rooms, rather than the technology corner, as part of our media trade. We consider it to be prime real estate, as pretty much everyone passes by the table at one time or another. People stopped by to chat; some just to ask where to find the registration desk, or the coffee, or in one instance, “are... »
Despite a valiant effort by the ECTC committee to integrate design topics into this year’s agenda, the number of empty seats spoke volumes: Including two plenary sessions on design-focused topics was one thing; getting packaging and process engineers to attend was quite another. While I attended IC Package Co-Design for HI Systems and AI and Its Impact on System Design, I have to admit, I found ... »
The special Tuesday session at ECTC 2018 took a look at new methods and applications for assembly technology to accommodate the needs of heterogeneous integration at the system level. The session was chaired by Florian Herrault, HRL Laboratories, and featured Jeff Demmin, DARPA; Stefan Behler, Besi; Matthew Meitl, X-celeprint; Doris Tang, PlayNitride; and Val Marinov, Uniquarta. Presentations offe... »
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