NEW DATE TBD – Accepting additional presentations – contact Rosina Haberl
With heterogeneous integration (HI) and advanced packaging becoming the dominant drivers of progress in many electronic products, the need for collaboration and a robust ecosystem has grown. In the earlier days of Moore’s Law when the silicon node was the main metric and driver for advances in the semiconductor industry, the International Technology Roadmap for Semiconductors (ITRS) was the primary vehicle for coordinating these activities.
Now, though, there is no single metric specifying the details and timing for progress enabled by integration technologies, so new approaches are needed. There have been road mapping efforts that have laid much of the groundwork, such as the Heterogeneous Integration Roadmap (HIR), but more work is needed to have such efforts fully embedded in the industry’s path forward. Similarly, there are various interconnect standards emerging, such as UCIe, but with more (and more complicated) integration scenarios, these standards cover only a fraction of what’s needed.
Microelectronics Packaging and Test Engineering Council (MEPTEC www.meptec.org) is hosting an in-person symposium later this fall to explore the challenges faced in creating a robust HI ecosystem. We will have speakers from throughout the semiconductor industry to help answer: What else can roadmaps do? How do we address the fundamentally different situation of heterogeneous integration compared to silicon nodes? Can we converge on a manageable set of standards, and what should be the scope of those standards? What other collaborative mechanisms will help the ecosystem? Given the collaborative approach needed to address the challenges, MEPTEC is very pleased to be presenting this as an in-person event. See you there!
We are seeking participation via technical presentations from commercial and academic domains. Topics of interest include, but are not limited to:
- Lessons learned from adjacent technology verticals (MEMS, sensors, etc.)
- Progress and lessons learned from consortiums (UCIe, PCIe, etc.)
- Meaningful product metrics
- Chiplet manufacturing, reliability, and test strategies in relation to standards & roadmaps
- Hard and soft intellectual property (IP) marketplaces
- Design and analysis approaches to enable Chiplet standards
- Manufacturing resources and infrastructure
We are also soliciting event sponsors to support the event.
Please submit your presentation abstract (150 to 250 words) to Rosina Haberl (firstname.lastname@example.org) no later than June 1, 2023. Or contact Rosina for additional information.