10/22/2019 - 10/24/2019 -12:00 am

Location: DoubleTree by Hilton San Jose

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SMTA and Chip Scale Review are pleased to announce the 16th Annual International Wafer-Level Packaging Conference and Tabletop Exhibition. IWLPC brings together some of the semiconductor industry’s most respected authorities addressing all aspects of wafer-level, 3D, TSV, and MEMS device packaging and manufacturing.

Registration is open here.

The Technical Program has been announced, along with keynote speakers. Keynotes will cover “The OSAT’s Dilemma and the Future”, “Slowdown: When Did it Start … What Drove it … When Will the Recovery Come”, and “A Borderless Future for Electronic Interconnect”.

Interconnecting Wafer-Level Packaging, 3D Packaging, Advanced Manufacturing and Test, the International Wafer-Level Packaging Conference (IWLPC) is at the forefront of the packaging technology evolution. The event will cover three separate tracks: Wafer-Level Packaging (WLP), t3D Packaging, and Advanced Manufacturing.