07/23/2014 -2:00 pm - 5:00 pm

Location: PMC-Sierra

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EDA vendors provide tools to decrease design cycle time and help ensure accuracy. Cadence, Mentor Graphics, and E-System Design will present tools support for 3D-IC design.


Opening Remarks

Cadence 3D-IC Tool Suite
Brandon Wang, Cadence

Verifying Physical Die-to-Die Alignment and Interconnect in 2.5D and 3D Systems,
John Ferguson, Mentor Graphics

Stacking of die from multiple processes can introduce a challenge to traditional physical verification processes. Traditional DRC, LVS and other verification components, assume vertical depth based on layer assignments in the layout. As such, all polygons on the same layer are considered to be co-planar. In the case of stacked die, it is possible for two separate die to have geometries on the same layer, but with different vertical heights. Treating these with traditional verification methods will no longer work. We present an automated approach to verify the appropriate die-to-die interactions without such limitations.

Role of Path Finding?
Bill Martin, E-System Design
3D integration is being touted as the next semiconductor revolution by industry. 3D integration involves the use of disparate interconnect structures that include balls, pillars, bond wires, through silicon vias (TSV) and redistribution layers (RDL) for enabling chip stacking, interposer and printed circuit board (PCB) based technologies. More recently 2.5D integration using silicon interposers is coming of age with wide I/O gaining steam for 3D integration. For such new integration schemes to be viable, mixing and matching of technologies are required to evaluate system performance early in the design cycle. The role of path finding is therefore to enable early exploration prior to implementation.

Working Group Project Discussion – 3D-IC ESD

Wrap-Up and Logistics

Webcast Information:
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Webcast: GSA Working Groups Meeting
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