07/13/2016 -5:30 pm

Location: NXP Semiconductors Discovery Business Center

Loading Map....

John-LauRecent advances in, e.g., fan-out wafer/panel level packaging (TSMC’s InFO-WLP and Fraunhofer IZM’s FO-PLP), 3D IC packaging (TSMC’s InFO_PoP vs. Samsung’s ePoP), 3D IC integration (Hynix/Samsung’s HBM for AMD/NVIDIA’s GPU vs. Micron’s HMC for Intel’s Knights Landing CPU), 2.5D IC Integration (TSV-less interconnects and interposers), embedded 3D hybrid integration (of VCSEL, driver, serializer, polymer waveguide, etc.), and 3D MEMS/IC integration will be discussed in this presentation. Emphasis is placed on various FOWLP formation methods such as chip-first with die up, chip-first with die-down, and chip-last (RDL-first). Since RDLs (redistribution layers) play an integral part of FOWLP, various RDL fabrication methods such as Cu damascene, polymer, and PCB (printed circuit board) will be discussed. A few notes and recommendations on wafer vs. panel, dielectric materials, and molding materials will be provided. Also, TSV-less interposers such as those given by Xilinx/SPIL, Amkor, Intel, ITRI, and Shinko will also be discussed.

Presenter: Dr. John H. Lau, Sr. Technical Advisor ASM Pacific Technology
With more than 35 years of R&D and manufacturing experience in semiconductor packaging, Dr. John H. Lau has published more than 440 peer-reviewed papers, 30 issued and pending patents, and 18 textbooks on, e.g., *Advanced MEMS Packaging* (McGraw-Hill Book Company, 2010), *Reliability of RoHS compliant 2D and 3D IC Interconnects* (McGraw-Hill Book Company, 2011), *TSV for 3D Integration*, (McGraw-Hill Book Company, 2013), and *3D IC Integration and Packaging* (McGraw-Hill Book Company, 2016). John’s current interests are in 3D IC integration and fan-out wafer- or panel-level packaging. He earned his Ph.D. degree from the University of Illinois – Urbana. Dr. John Lau is an elected ASME Fellow and has been an IEEE Fellow since 1994. Dr. John H. Lau is a CPMT Society Technical Field Award recipient in 2013 “*For contributions to the literature in advanced solder materials, manufacturing for highly reliable electronic products, and education in advanced packaging.”

  • 5:30–6:00 PM: Social/Refreshments,
  • 6:00–7:00 PM: Presentation
  • 7:00 PM: Dinner (Pizza and Soda will be provided by the IEEE Phoenix Section CPMT Society Chapter)

IEEE members and non-members are all welcome to attend. The presentation
promptly starts at 6:00 PM.

For more information, please contact any of the following CPMT officers:

  • Vasu Atluri (480) 227-8411
  • Rao Bonda (480) 786-7749
  • David Dougherty (480) 413-6923
  • Vivek Gupta (480) 734-0266
  • Marc Licciardi (650) 996-0478
  • Ravi Mahajan (480) 554-3715
  • Bharat Penmecha (480) 552-2511
  • Mahesh Shah (480) 544-9438
  • Shawn Shi (480) 929-5614