Technologies Features

Lithography Process Innovations Part 2: Improving Thermo-mechanical Reliability of TSV Interconnects

Lithography Process Innovations Part 2: Improving Thermo-mechanical Reliability of TSV Interconnects

In Part 1 of this article series, we noted that despite the potential benefits associated with 3D and interposer-based 2.5D designs, the incorporation of TSVs poses significant challenges to the performance and reliability of 3D wafer level packages (3D WLP). Among these is the generation of TSV stress in 2.5D/3D packaging – both thermal-induced stress resulting from the coefficient of thermal e... »

Lithography Process Innovations for 2.5/3D Part 1: Alleviating TSV Stress

Lithography Process Innovations for 2.5/3D Part 1: Alleviating TSV Stress

As traditional semiconductor scaling becomes increasingly complex and cost-prohibitive, transitioning from planar chip packaging architectures to 2.5D/3D stacked die package architectures has become key to enable the integration of greater amounts of chip functionality in smaller form factors. This need for form factor reduction, together with smaller process geometries and higher-count I/O on int... »

Low-Temp, Ultra-Fine-Pitch Cu Interconnections for Manufacturable, Solder-free Assembly

Low-Temp, Ultra-Fine-Pitch Cu Interconnections for Manufacturable, Solder-free Assembly

A novel copper interconnection technology is being pioneered by Georgia Tech’s Packaging Research Center (GT-PRC) to achieve manufacturable solder-free assembly at low temperatures. By interfacing engineering and process design, the Cu interconnections are shown to meet both thermal cycling and ultra-high current-handling needs. This technology is now being applied to mobile and high-perfor... »

TSV MEOL Process Flow for Mobile 3D IC Stacking

TSV MEOL Process Flow for Mobile 3D IC Stacking

Moore’s law is approaching physical limitations of CMOS scaling, and three dimensional (3D) integration technologies have been proposed as solutions. Wide band transmission between logic and memory is becoming indispensable for not only mobile products, but also other products related to network systems such as servers and data centers. These days, 3D integration with Through Silicon Vias (T... »

Path Finding: Who Performs and When?

Path Finding: Who Performs and When?

Microelectronic products all have mechanical, thermal and electrical properties that degrade until the device is permanently damaged. Path finding adds value to an end-product by pre-determining where the breaking points are, and if or how they can be enlarged. For decades, product designers have used various methods of path finding to determine optimum solutions for the design and manufacture of ... »

2.5/3D Packaging: Path Finding

2.5/3D Packaging: Path Finding

2.5D/3D packaging technologies are revitalizing creativity in high technology products. We thought we knew what faster, better, lighter and smaller meant. 2.5D/3D packaging can revolutionize what we thought possible but it will require augmenting our current methods and tools. One key methodology to add would be Path Finding. Path Finding can ensure a design’s structural integrity early in the... »

3D IC System Verification Methodology: Solutions and Challenges

3D IC System Verification Methodology: Solutions and Challenges

By Dusan Petranovic, Member, IEEE, and, Karen Chow, Member, IEEE, (Mentor Graphics) The three largest EDA companies are taking an evolutionary, rather than a revolutionary, approach in developing the 3D IC design tools. This appears to be a good decision because the technology, the rules and the standards are still evolving. The main EDA challenges are expected in the design space exploration [6]... »

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