Technologies Features

The Commercialization of 3D Stackable Memory: Part One

The Commercialization of 3D Stackable Memory: Part One

The Challenges of Manufacturing 3D Stackable Memory Memory technologies vying to fulfill the increasing capacity and density requirements of the solid-state storage market two years from now will be confronted by having to meet demanding cell performance and cost-per-bit metrics to be viable. Today, NAND technology is still the primary solution for building solid-state storage devices (SSD), as th... »

Comparing Two Flavors of Chip Stacking Yield

Comparing Two Flavors of Chip Stacking Yield

One of the ways to build more complex, powerful, and cost-effective electronic systems is stacking chips on top of each other. Imec recently compared the two main options for going 3D: interposer-based stacking and 3D stacking. The goal of the exercise was to detect whether the stacking and packaging processes for the two options result in a different yield, and where in the processes those differ... »

Wafer-to-Wafer Bonding Cost Analysis

Wafer-to-Wafer Bonding Cost Analysis

Last year, I did an analysis that included the topic of wafer-to-wafer bonding. Specifically, it was a comparison of the three variations available when stacking wafers and/or die—wafer-to-wafer (W2W), die-to-wafer (D2W), and die-to-die (D2D). The goal of that project was to build cost models for W2W and D2W (with the understanding that D2D had similar cost drivers to D2W), and perform a compari... »

CoolCube™: A True 3DVLSI Alternative to Scaling

CoolCube™: A True 3DVLSI Alternative to Scaling

Stacking transistors on top of each other sequentially in the same front-end process flow is a concept that has been imagined to provide the semiconductor community with an alternative to the traditional scaling paradigm challenged by technical and cost roadblocks. LETI Advanced CMOS Laboratory introduced CoolCube™, a low-temperature process flow that provides a true path to 3DVLSI. »

Technology Options and Their Influence on Routing for Interposer-based Memory Processor Integration

Technology Options and Their Influence on Routing for Interposer-based Memory Processor Integration

Currently  in advanced integration, mainly stacked solutions (Figure 1b) are considered due to their attractive compactness. But if the ASIC or the processor is a high-performance circuit, there are problems with the thermal budget of the stacked solution. This is because the valid temperature range of the memory is limited. Designing a thermally balanced solution is very challenging and often en... »

Understanding Heterogeneous 3D Integration

Understanding Heterogeneous 3D Integration

“How is heterogeneous 3D integration defined?” There are certainly different understandings in the microelectronics community regarding the definition of heterogenous 3D integration. In a very general definition, it is defined as the 3D integration of different devices such as a CMOS processor and a memory, for example. A more limiting specification would define it as the integration of dif... »

The Cost of 3D ICs

The Cost of 3D ICs

When 3D integration has been discussed in the past, whether in terms of a true 3D IC stack or an interposer-based design, the cost of 3D ICs has not always been part of the discussion. In the past couple of years, as 3D ICs have moved closer to reality, more attention has finally been turned to cost. Sometimes the only comment is that ‘cost will come down’ because cost always seems to come do... »

Addressing 3D Integration Challenges: Designing Materials for a Complex Landscape

Addressing 3D Integration Challenges: Designing Materials for a Complex Landscape

3D integration has created a complex landscape of many different package architectures and integration approaches that have diverse materials needs and uncertain insertion timing. The multitude of processes required do not fit neatly into the established pigeonholes of front-end and back-end. Processes such as through silicon via (TSV) fabrication require wafer processing equipment, materials and ... »

Lithography Challenges for 2.5D Interposer Manufacturing

Lithography Challenges for 2.5D Interposer Manufacturing

In recent years, 2.5D packaging has quickly gained acceptance as an advanced packaging process, and the first products using this technology are now coming to market.¹ Most estimates project growth for 2.5D interposer packaging faster than the industry as a whole. Similar to the multi-chip modules (MCMs) of the past, 2.5D packaging processes use an interposer with vias connecting the metallizatio... »

Glass Substrates for Advanced Packaging

Glass Substrates for Advanced Packaging

Glass has many properties that make it an ideal substrate for interposers such as: ultra-high resistivity and low electrical loss, low dielectric constant, and adjustable coefficient of thermal expansion (CTE). Leveraging glass-forming processes such as Corning’s fusion forming process provides roughness < 0.5nm rms, and flat substrates with good stiffness. These properties provide opportunit... »

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