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MEPTEC Roadmap 2016: Best Time in History to be in the Packaging Business

MEPTEC Roadmap 2016: Best Time in History to be in the Packaging Business

With nary a farewell glance in the rearview mirror at the terrain successfully covered over the decades during which we followed the ITRS’ Guide Michelin; the new Heterogeneous Integration Roadmap gives us eyes on what comes next. It looks from here-and-now all the way to a horizon that extends, like a straight highway crossing America’s vast Great Plains, a long way out. Fifteen years out. A ... »

At the Crossroads of CVD and ALD, KOBUS Makes its Mark on 3D TSVs

At the Crossroads of CVD and ALD, KOBUS Makes its Mark on 3D TSVs

Last July at SEMICON West, I was honored to witness the dramatic unveiling of UnitySC, the new company formed as a result of Fogale Group’s acquisition of Altatech, resulting in a semiconductor equipment portfolio that spans the spectrum of process control needs for advanced wafer-level and 3D packaging, including metrology, edge inspection, and defect detection. But that was only part of the st... »

SEMICON Europa 2017 Moves to Munich

SEMICON Europa 2017 Moves to Munich

So here’s a funny story.  At the MEMS Summit in Stuttgart in September, while chatting with Denny McGuirk President and CEO, SEMI, I suggested that SEMICON Europa 2017 would be better attended if it was held in Munich. I’ll admit this was mostly selfishly motivated, as I’ve made the trek from Phoenix to Dresden and Grenoble for industry events, and it’s not an easy one. (Full disc... »

First-Mover Advantage: Fan-Out Panel Level Packaging at IWLPC 2016

First-Mover Advantage: Fan-Out Panel Level Packaging at IWLPC 2016

“It is better to be first than it is to be better.” (Ries and Trout, in The 22 Immutable Laws of Marketing.) Or is it “Fast Followers Not First Movers Are The Real Winners?” Fan-Out Wafer Level Packaging has built up such a head of steam this year (see “iPhone 7: Apple Charts a Strategic Course by Selecting TSMC’s inFO Platform”) that backwards reels the mind thinking about what come... »

Pasadena offers Roses and Technology

Pasadena offers Roses and Technology

California’s Pasadena is well known for the New Year Rose Parade and the Rose Bowl. There is no doubt: It takes commitment and organizational talent to make these events successful for 100+ years, and encourage every contributor to prepare and execute successful events every year. Last week’s International Microelectronics Assembly and Packaging Solutions Conference (iMAPS) in Pasadena’s Con... »

At the 2016 S3S Conference, 3D Integration is Bringing Sexy Back

At the 2016 S3S Conference, 3D Integration is Bringing Sexy Back

The IEEE S3S Conference (shorthand for the IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference; quite a mouthful, I know!) is an annual gathering of an intimate crowd (generally 100-125 attendees) that for 35 years has been the premier meeting of engineers and scientists dedicated to current trends in Silicon-On-Insulators (SOI) technology. A parallel 3D integration track was a... »

Image Courtesy of TSMC Ltd.

TSMC’s OIP Symposium 2016

After a fairly long vacation it’s very hard to get back to work. That’s why I was really glad that this year’s OIP Symposium helped me – right after touring Europe for 3 weeks – to finding my groove again. Allow me to share some of my observations at and thoughts about the Symposium, from my “More-than-Moore EcoSystem builder” perspective. The collaborative innovation programs TSMC ... »

Gartner: New Normal is Slow Growth, Plentiful FOWLP

Gartner: New Normal is Slow Growth, Plentiful FOWLP

What is the “new normal” for semiconductors? Jim Walker, Research VP, Semiconductor Manufacturing, Gartner, closed out Q3 2016 with his informative talk at the IMAPS | MEPTEC | SEMI Northern California Chapter luncheon meeting on September 28, 2016, at SEMI HQ in San Jose, California, addressing the topic of the “New Normal” for Semiconductors. Remember diagraming P.E.S.T analyses ... »

Will The Lifespan of CMOS Integrated Circuits End?

There is fierce competition for scaling foundry logic technologies. However, according to the 2015 International Roadmap for Semiconductors (ITRS), logic transistor scaling will stop at 10nm and it will no longer be economically desirable for companies to continue traditional transistor miniaturization in microprocessors1. How will this impact the lifespan of CMOS integrated circuits? (Figure 1)... »

More Food for Thought From The 2016 European MEMS Summit

More Food for Thought From The 2016 European MEMS Summit

Granted, while there may not have been a single “aha!” moment at the 2016 European MEMS Summit, held September 15-16 in Stuttgart Germany, the speakers did provide interesting food for thought as they talked about their companies’ activities and offerings in MEMS and sensor technology. 2016 European MEMS Summit from 3D InCites on Vimeo. In addition to the summary I posted earlier this week,... »

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