Just under a week away, the agenda for the 2017 IMAPS Device Packaging Conference and co-located Global Business Council is geared to inspire attendees about the growing importance of heterogeneous integration technologies supported by advanced wafer level packaging, 2.5D, and 3D integration. While the quest for smaller silicon nodes continues, it’s well understood that these technologies are fi... »
The data traffic explosion, fueled by the Internet of Things (IoT), social media and server applications, has created a need for ever-advancing semiconductor technologies. Servers, mobile devices, IoT devices… they drive the requirements for semiconductors’ future processing and storage capacity. But will we be able to continue traditional semiconductor scaling, as initiated by Gordon Moor... »
There is an active and robust supply chain currently supporting these wafer sizes in the semiconductor manufacturing industry: 3”; 4”; 6”; 200mm; 300mm; and 330mm. This wide range of substrates is successfully being used today for “sweet-spot’ manufacturing of LED, compound semiconductor, MEMS, trailing-edge CMOS, leading-edge CMOS, and fan-out wafer level packaging (FOWLP) applications,... »
Grenoble, France – UnitySC, a wholly owned subsidiary of FOGALE Nanotech Group and a leader in inspection and metrology solutions for advanced semiconductor packaging, today announced the opening of its global headquarters in Grenoble, France, the heart of the French Silicon Valley. This location strategically positions the company in one of Europe’s key semiconductor research and manufacturi... »
It’s 2017, and system-on-a-chip (SoC) is headed for a dielet. At least that’s my 2017 outlook, based on takeaways from some of the recent conferences I’ve attended, including, to close out 2016, 3D ASIP last month in Burlingame, CA. SoC has been packing on weight in recent years, and it’s beginning to show, to SoC’s detriment. For example, the old ISO defect density rules from my early I... »
Sorry everybody, but I couldn’t resist this Buzzfeed-esque title, because Besi’s Hugo Pristauz’ unprecedented use of “colorful” language to illustrate the “turbulent plane ride” of ramping thermo-compression bonding die attach to volume production just might go down in history as the most talked (and laughed) about incident at the 2016 3D Architectures for Semiconductor I... »
The embedded-die-in-substrate platform has its own history and adoption scheme compared to other advanced packaging platforms, explains Yole Développement (Yole). Indeed while the first significant volume of embedded die in integrated circuit (IC) package substrates came from direct current (DC) converters in smartphones, penetration in other market segments of interest to embedded die such as au... »
In the past few months I have been reading a lot of depressing news about our semiconductor industry’s declining growth rates, shrinking profit margins, many consolidations, as well as many articles about why, when and how following Moore’s Law will be only justified for extremely high-volume designs. Sounds kind of depressing and worrisome for semiconductors, however, last week’s Internatio... »
In less than two weeks, the 13th Annual Architectures for Semiconductor Integration and Packaging Conference (3D ASIP) kicks off at the Marriott San Francisco Airport, this year under the auspices of the International Microelectronics and Packaging Society (IMAPS). Long heralded as THE conference for 2.5D and 3D integration, the conference was created by the Tech Venture Forum at RTI International... »
For the fifth consecutive year, the European 3D Summit returns to Grenoble, January 23-25, 2017. The event has evolved over those years, beginning its tenure as the 3D TSV Summit, then last year re-branded as the 3D Summit in acknowledgment that not everything in 3D has to do with through silicon vias (TSVs). I’ve been honored to attend the four previous years, and have found the event to consis... »
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