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Heterogeneous Integration Makes an End Run Around 7nm Silicon at SEMI ASMC 2017

Heterogeneous Integration Makes an End Run Around 7nm Silicon at SEMI ASMC 2017

I like to think that someday soon a perfectly ripe tomato growing on a vine is going to signal its condition via the 5G network to an AI who knows I love heirloom tomatoes at their peak; my AI will place an order for me based on standing instructions (after first confirming I am indeed expected home that evening, and that I already don’t have too many heirlooms on the counter), and an autonomous... »

MEMS  Ascendant at IMAPS Device Packaging 2017

MEMS Ascendant at IMAPS Device Packaging 2017

Semiconductor device fabrication and packaging is rife with acronyms, and by my estimate, the Top 3 trafficked by speakers at the recent IMAPS Device Packaging Conference were the acronyms FOWLP, FOPLP, and MEMS. That would be fan-out wafer level packaging, fan-out panel level packaging, and microelectromechanical systems, respectively. It wasn’t that IMAPS was a MEMS packaging conference in the... »

Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging

Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging

In recent years, there has been an increased focus on fan-out wafer level packaging. While fan-out wafer level packaging may be the right solution for some designs, it is not always the lowest cost solution. Flip chip packaging, a more mature technology, continues to be an alternative to fan-out wafer level packaging. Both technologies are suitable for many of the same applications, and it is impo... »

MRSI Systems Delivered 3-Micron Die Bonder to AIM Photonics Academy’s Education and Practice Factory at MIT

MRSI Systems Delivered 3-Micron Die Bonder to AIM Photonics Academy’s Education and Practice Factory at MIT

North Billerica, MA, USA, March 20, 2017 — MRSI Systems, a leading provider of fully automated, high-speed, high-precision die bonding and epoxy dispensing systems, today announces the installation of its flagship MRSI-M3 Die Bonder in AIM Photonics Academy’s Education and Practice Factory at the Massachusetts Institute of Technology (MIT) in Cambridge, MA, USA. This is the beginning of a grea... »

UnitySC Pushes The Boundaries of Measurement with New Nanotopography Metrology Platform

UnitySC Pushes The Boundaries of Measurement with New Nanotopography Metrology Platform

Grenoble, France, March 14, 2017 – UnitySC, a wholly owned subsidiary of FOGALE Nanotech Group and a leader in inspection and metrology solutions for advanced semiconductor packaging, today introduced its new NST Series at SEMICON China in Shanghai. The NST Series is the world’s first non-contact metrology solution for accurately measuring the nanoscale surface topography of semiconductor wafe... »

What’s in Store For You at IMAPS DPC 2017

What’s in Store For You at IMAPS DPC 2017

Just under a week away, the agenda for the 2017 IMAPS Device Packaging Conference and co-located Global Business Council is geared to inspire attendees about the growing importance of heterogeneous integration technologies supported by advanced wafer level packaging, 2.5D, and 3D integration. While the quest for smaller silicon nodes continues, it’s well understood that these technologies are fi... »

Finding The Next Switch for Semiconductor Scaling

Finding The Next Switch for Semiconductor Scaling

The data traffic explosion, fueled by the Internet of Things (IoT), social media and server applications, has created a need for ever-advancing semiconductor technologies. Servers, mobile devices, IoT devices… they drive the requirements for semiconductors’ future processing and storage capacity. But will we be able to continue traditional semiconductor scaling, as initiated by Gordon Moor... »

Panel Level Packaging: One Size Fits All?

Panel Level Packaging: One Size Fits All?

There is an active and robust supply chain currently supporting these wafer sizes in the semiconductor manufacturing industry: 3”; 4”; 6”; 200mm; 300mm; and 330mm. This wide range of substrates is successfully being used today for “sweet-spot’ manufacturing of LED, compound semiconductor, MEMS, trailing-edge CMOS, leading-edge CMOS, and fan-out wafer level packaging (FOWLP) applications,... »

FOGALE Nanotech Group Subsidiary UnitySC Opens New Global Headquarters in Grenoble, France

FOGALE Nanotech Group Subsidiary UnitySC Opens New Global Headquarters in Grenoble, France

Grenoble, France – UnitySC, a wholly owned subsidiary of FOGALE Nanotech Group and a leader in inspection and metrology solutions for advanced semiconductor packaging, today announced the opening of its global headquarters in Grenoble, France, the heart of the French Silicon Valley. This location strategically positions the company in one of Europe’s key semiconductor research and manufacturi... »

Outlook 2017:  SoC Goes on a Dielet

Outlook 2017: SoC Goes on a Dielet

It’s 2017, and system-on-a-chip (SoC) is headed for a dielet. At least that’s my 2017 outlook, based on takeaways from some of the recent conferences I’ve attended, including, to close out 2016, 3D ASIP last month in Burlingame, CA. SoC has been packing on weight in recent years, and it’s beginning to show, to SoC’s detriment. For example, the old ISO defect density rules from my early I... »

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