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A Material Solution for the Growing 3D Imaging Market

A Material Solution for the Growing 3D Imaging Market

With emerging markets developing for augmented reality (AR), virtual reality (VR), facial-recognition security systems, advanced human/machine interfaces and other 3D imaging applications, the need for 3D camera systems is booming. These 3D cameras require CMOS image sensors that are capable of working in the near-infrared (NIR) spectrum. In 2018, a towering wave of 3D imaging and sensing products... »

Is MEMS Packaging and Test the Next Opportunity for OSATs?

Is MEMS Packaging and Test the Next Opportunity for OSATs?

More than half of microelectromechanical systems MEMS packaging today is done by outsourced semiconductor and test services providers (OSATs) and Yole Développement (Yole) estimates OSATs’ market share will continue to grow in the next five years. The MEMS volume augmentation, especially for radio frequency (RF) applications, is making the MEMS business more and more attractive for OSATs, which... »

IEDM 2017 Looks Way Beyond Moore’s Law

IEDM 2017 Looks Way Beyond Moore’s Law

The International Electronic Device Manufacturing Conference (IEDM) has always focused on device scaling, successfully guiding our industry for several decades along the challenging paths of Moore’s Law and the ITRS Roadmap. Both were primarily focused on digital functions. However, we all must agree that the real world around us is analog. To allow our electronic devices to better assist us in... »

3D InCites and IMAPS International Partner to Co-host the 2018 3DInCites Awards at the 2018 IMAPS Device Packaging Conference

3D InCites and IMAPS International Partner to Co-host the 2018 3DInCites Awards at the 2018 IMAPS Device Packaging Conference

Burlingame, California – Dec. 6, 2018 – 3D InCites, the premier content platform for heterogeneous integration technologies, today from the 2017 3D ASIP Conference, announced a collaboration with IMAPS International to co-host the 2018 3D InCites Awards, the semiconductor industry’s most prestigious award program recognizing contributions for the development of heterogeneous integration tech... »

A Tribute to Gilles Poupon, CEA-Leti’s Advanced Packaging Pope

A Tribute to Gilles Poupon, CEA-Leti’s Advanced Packaging Pope

Sitting in the bus on the way back from Grenoble to Airport Lyon, I am reflecting the last two days during which we honored Gilles Poupon, the Advanced Packaging “Pope” of CEA Leti. Upon his retirement at the end of November 2017, somehow an era ends. I have known Gilles for quite a long time: He reminded of the first time we met. It was 2003 in Munich. Gilles was a member of the CEA delegatio... »

Heterogeneous Integration Makes an End Run Around 7nm Silicon at SEMI ASMC 2017

Heterogeneous Integration Makes an End Run Around 7nm Silicon at SEMI ASMC 2017

I like to think that someday soon a perfectly ripe tomato growing on a vine is going to signal its condition via the 5G network to an AI who knows I love heirloom tomatoes at their peak; my AI will place an order for me based on standing instructions (after first confirming I am indeed expected home that evening, and that I already don’t have too many heirlooms on the counter), and an autonomous... »

MEMS  Ascendant at IMAPS Device Packaging 2017

MEMS Ascendant at IMAPS Device Packaging 2017

Semiconductor device fabrication and packaging is rife with acronyms, and by my estimate, the Top 3 trafficked by speakers at the recent IMAPS Device Packaging Conference were the acronyms FOWLP, FOPLP, and MEMS. That would be fan-out wafer level packaging, fan-out panel level packaging, and microelectromechanical systems, respectively. It wasn’t that IMAPS was a MEMS packaging conference in the... »

Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging

Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging

In recent years, there has been an increased focus on fan-out wafer level packaging. While fan-out wafer level packaging may be the right solution for some designs, it is not always the lowest cost solution. Flip chip packaging, a more mature technology, continues to be an alternative to fan-out wafer level packaging. Both technologies are suitable for many of the same applications, and it is impo... »

MRSI Systems Delivered 3-Micron Die Bonder to AIM Photonics Academy’s Education and Practice Factory at MIT

MRSI Systems Delivered 3-Micron Die Bonder to AIM Photonics Academy’s Education and Practice Factory at MIT

North Billerica, MA, USA, March 20, 2017 — MRSI Systems, a leading provider of fully automated, high-speed, high-precision die bonding and epoxy dispensing systems, today announces the installation of its flagship MRSI-M3 Die Bonder in AIM Photonics Academy’s Education and Practice Factory at the Massachusetts Institute of Technology (MIT) in Cambridge, MA, USA. This is the beginning of a grea... »

UnitySC Pushes The Boundaries of Measurement with New Nanotopography Metrology Platform

UnitySC Pushes The Boundaries of Measurement with New Nanotopography Metrology Platform

Grenoble, France, March 14, 2017 – UnitySC, a wholly owned subsidiary of FOGALE Nanotech Group and a leader in inspection and metrology solutions for advanced semiconductor packaging, today introduced its new NST Series at SEMICON China in Shanghai. The NST Series is the world’s first non-contact metrology solution for accurately measuring the nanoscale surface topography of semiconductor wafe... »

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