3D by Design

PDN Design, Target Impedance and Path Finding for IC, Package, and PCB

PDN Design, Target Impedance and Path Finding for IC, Package, and PCB

I am fortunate to work with Prof. Madhavan Swaminathan, Founder, CTO, E-System Design, and inventor of our algorithms. Long ago, as an undergraduate engineering student at University of Illinois focused on integrated circuit (IC) design, I enrolled in the required ElectroMagnetics (EM) course to discover it was all about large antennas¹. At that time, silicon and EM classes were not synchronized ... »

Assembly Design Kits are the Future of Package Design Verification

Assembly Design Kits are the Future of Package Design Verification

Unlike the traditional system-on-chip (SoC) design process, which has fully qualified verification methods embodied in the form of process design kits (PDKs), chip design companies and assembly houses have no integrated circuit (IC) package co-design sign-off verification process to help ensure that an IC package will meet manufacturability and performance requirements. Package die are often produ... »

Path Finding and 3DPF

Path Finding and 3DPF

In the past year, I have written short pieces explaining how Path Finding methodology can proactively help identify viable solutions or reactively identify solutions if something changes during manufacturing. The next few blogs will look at specific examples using a PF tool to help separate the ‘wheat from the chaff’. Signal Assignments When I was designing ASICs/SOCs at VLSI Technology, we no... »

DAC 2015 Focuses on the Automotive Market

DAC 2015 Focuses on the Automotive Market

By attracting 7011 EDA and IP developers and users, the 52 Design Automation Conference, held in the South Hall of San Francisco’s Moscone Center in the week of June 7, achieved a 14.5% increase in attendees. I was one of them, and started on Sunday evening by listening to Gary Smith’ EDA Forecast presentation. Based on Gary’s and Laurie Blach’s analysis, EDA is likely to grow by 11.2 % ... »

Who Should Win the First 3D InCites Individual Achievement Award?

Who Should Win the First 3D InCites Individual Achievement Award?

The journey to the commercialization of 3D integration technologies has been long – longer than most expected – an arduous. It has required tremendous investment, and it has required the efforts of the entire supply chain. The industry has experienced a paradigm shift in how it conducts business because of it. There has been an increase in communication and collaboration, and the walls... »

How to Ensure Quality and Reliability in 3D IC stacks

How to Ensure Quality and Reliability in 3D IC stacks

A major concern in 3D IC designs is ensuring reliability and quality. Specifically, there is a growing need for design verification flows that can determine the cross-layer implications of the stresses caused by through silicon vias (TSVs) and chip-package interaction (CPI) induced mechanical stresses. Because 3D IC stacks have limited access for characterization and measurement, yet have a strict... »

Is Complex Packaging in High Volume Manufacturing (HVM)?

Is Complex Packaging in High Volume Manufacturing (HVM)?

Over the past year… The amount of 2.5/3D articles published has gained momentum. Some articles discuss when HVM will be achieved for this complex packaging, others discuss costs from chip to system levels, how to evaluate options, design and verify, etc. All articles are based on facts gleaned from various articles, presentations and conferences that authors have viewed or participated in. The... »

Can Path Finding be used in the Production Environment?

Can Path Finding be used in the Production Environment?

In previous posts, I have discussed various scenarios when Path Finding can be used. All were focused on the early design process: implementation guidelines, robust design and process centering. But what if you have a design in production and ‘something’ happens; like a process is no longer available; a component must be replaced by another, yields become erratic, etc. Is there a role for Path... »

Silicon Photonics and 2.5D Interposer Design

Silicon Photonics and 2.5D Interposer Design

Historically, we all took Moore’s Law for granted. With each new node, we could expect to see faster-performing devices, smaller design footprints and, ultimately, lower design costs. Nowadays these benefits are not clearly achievable for all designers. At the latest advanced technology nodes, we may be able to see faster devices through the miracles of finFET technologies, but do we really get ... »

Micro vs. Macro 3D IC Cost Analysis: Can we learn from the mid 1980’s?

Micro vs. Macro 3D IC Cost Analysis: Can we learn from the mid 1980’s?

Amy Palesko from SavanSys Solutions wrote an excellent 3D IC cost analysis article (The Cost of 3D ICs) on 3D InCites that focused on the manufacturing cost of TSV enabled devices. No question that these costs are important and will follow a classical manufacturing learning curve. But the real story is at the macro level or system costs using the new technologies. Introduction of ASIC designs…. ... »

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