Awards-Winner

Mentor Graphics: Xpedition Package Integrator

Mentor Graphics: Xpedition Package Integrator

Xpedition® Package Integrator provides a holistic co-design methodology that automates planning and optimization of connectivity from a chip through multiple packaging variables, while targeting multiple PCB platforms. Engineers can quickly and easily assemble complete cross-domain systems (IC, package & board) and drive ball map plans and pin optimization through a rule-based methodology. Te... »

Dow Corning: Thermally Conductive Gel TC-3040

Dow Corning: Thermally Conductive Gel TC-3040

TC-3040 is designed for advanced flip chip devices requiring improved heat dissipation.  The material features a combination of low modulus and high elongation – enabling it to accommodate warpage-induced stresses.  Key to the improved thermal performance : low contact resistance that silicones are known for, along with proprietary filler technology. Testimonial While advanced 2.5D or 3D... »

KLA-Tencor: CIRCL-AP™

KLA-Tencor: CIRCL-AP™

CIRCL-AP™ is a cluster tool with multiple modules, covering all-surface inspection, metrology and review at high throughput for efficient advanced wafer level packaging (AWLP) process control. The CIRCL-AP provides production-proven, high sensitivity monitoring capability for multiple AWLP applications including 2.5D/3D integration, wafer-level chip scale packaging and fan-out wafer-level packag... »

Amkor: SLIM

Amkor: SLIM

Amkor’s SLIM (siliconless integrated module) is a dies-last package technology providing the thinnest possible form factor with the highest level of integration by use of back-end-of-line technology combined with assembly-based fan-out architectures.  It has optimal registration, 3D access to top and bottom side of package and the finest line RDL capability found in packaging today! Testim... »

Xilinx: Ultrascale VU440 3D FPGA

Xilinx: Ultrascale VU440 3D FPGA

The Xilinx Ultrascale VU440 3D FPGA is constructed using “Xinterposer” 3D IC technology jointly developed by Xilinx and TSMC. It uses a low-k dielectric chip fabricated on 20nm silicon node with a total of 375,000 micron bumps stacked on 25mm x 45mm silicon interposer and assembled with CoWoS. The composite 3D FPGA consists of approximately 19 billion transistors. Testimonial: The Ultrasca... »

EV Group: GEMINI®FB XT Automated Production Fusion Bonding System

EV Group: GEMINI®FB XT Automated Production Fusion Bonding System

The GEMINI®FB XT fusion wafer bonding platform features up to a 3X improvement in wafer-to-wafer bond alignment accuracy as well as a 50% increase in throughput over the previous industry benchmark platform. These performance breakthroughs clear several key hurdles to the industry’s adoption of 3D-IC/TSV technology. Testimonial According to the ITRS, high-density TSV applications require wa... »