Standards

3D Workshop Panel Discussion Focuses on 3D Standards and EDA Tool Readiness

3D Workshop Panel Discussion Focuses on 3D Standards and EDA Tool Readiness

 Are slow standardization and CAD-tool development hindering the progress of 3D IC design and integration? This was the topic of discussion during the Friday 3D Workshop at DATE 2014, which took place this year in Dresden, March 28, 2014. I was invited to moderate this panel discussion, which featured panelists from EDA suppliers, industry, and academia. We wanted to mix it up a bit and involve ... »

Making Progress with 3D IC Design and Test

Making Progress with 3D IC Design and Test

Thank you, Ann Steffora Mutschler (Semiconductor Engineering) for getting to the bottom of the difference of EDA tools for  2.5D and 3D IC design and test, and providing such a clear explanation in your post, “Evolution vs. Revolution”. In this 2-part post, Mutschler explores the EDA vendor arguments that “tool and design flow changes need to be evolutionary, rather than revolutionary.” A... »

Donning my 3D Glasses at the MEPTEC Semiconductor Roadmap Symposium

Donning my 3D Glasses at the MEPTEC Semiconductor Roadmap Symposium

I admit, I always have my 3D glasses on at conferences. But even though the title of this week’s MEPTEC event was “The Semiconductor Roadmap Symposium, A Collaborative Update From Standards Bodies, Industry Groups and the Entire Supply Chain”, it could have been “3D TSVs Roadmap Symposium…” based on the direction the panel discussions took throughout the day. Not that I’m complainin... »

Silicon Photonics: the Next Killer App for 3D ICs? and more from the R&D Community

Silicon Photonics: the Next Killer App for 3D ICs? and more from the R&D Community

First it was going to be memory stacks, then it was Wide I/O DRAM on Memory, and now, as commercialization of 3D ICs gets pushed out further, will it be Silicon Photonics that drives 3D ICs to volume manufacturing? That was the opinion expressed by Michael Liehr, executive VP of Executive VP CNSE, during the SEMICON West 2013 R&D Panel – “A Conversation on the Future of Semiconductor Techn... »

Semi Trade Pubs Talk 3D, Just in time for SEMICON West

Semi Trade Pubs Talk 3D, Just in time for SEMICON West

That Jan Vardaman, she’s so clever! I just finished reading her column on ECTC 2013 in Printed Circuit Design and Fab, and thought her quippy, Las Vegas-y references in the opening paragraph were right on the money. Vardaman’s take on ECTC was similar to my own, discussed here in my review of the foundry panel session.  She also offers some great take-aways from some of the sessions that I m... »

image courtesy of Future Fab International

2.5D Products and 3DIC Standards and Roadmaps Are On the Move

Naysayers be damned! Full commercialization for 3D ICs in smartphones may be a few years out, but that doesn’t dampen the spirits of the truly devoted, who latch on to every forward step as a monumental accomplishment. This week, progress appears to be taking off for 2.5D products, and the roadmaps and standards area are making notable progress. (If you can get excited about that, than you are a... »

HMC Progress, More on Moore’s Law, and the GlobalFoundries’ Buzz

HMC Progress, More on Moore’s Law, and the GlobalFoundries’ Buzz

Not long after posting 3D IC Reality Check on Tuesday, I discovered that I missed one. If you haven’t read the post by SemiMD’s Mark Lepedus, Industry Inches Towards 3D Chips  you should. While its got some similar information about recent announcements from GlobalFoundries as was in Rick Merritt’s post in EETIMES, it has a much more optimistic spin. LePedus also gives a glimpse of ... »

3D TSVs: Will Europe Lead the Way?

The first European 3D TSV Summit (January 22-23, 2013) hasn’t even happened yet, and already its intended message is becoming clear: Europe is ready to tackle those remaining issues and lead the world down the home stretch. It makes sense, since Europe’s R&D centers (imec, CEA Leti, Fraunhofer IZM) has been leading the way from the beginning, its foundries and IDMs (ST Microelectronics an... »

2.5D and 3D FPGA Update

Ever since TSMCs Open Innovation Platform (OIP) event, we’ve been hearing all about how the company has qualified its 2.5D chip-on-wafer-on-substrate (CoWoS) process flow, announced its test vehicle, and has begun shipping products. Indeed, at Roadmaps for Multi-die Packaging (November 14, 2012) Jan Vardaman used Altera’s adoption of the CoWoS test vehicle and design guidelines as an example ... »

SEMICON Europa 2012 Focuses on Materials, 3D ICs, and 450mm

SEMICON Europa got underway yesterday, and reports from the event point to new materials, 450mm and 3D ICs as the key topics – all from the European perspective. According to SEMI Europe President, Heinz Kundert, Europe has reached a critical crossroads where its very future as a global competitor seems to hinge on making it in micro- and nano-electronics. "Europe must not risk the walking away ... »

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