Innovating Through Precision and Speed: How Laser Etching Is Redefining RF Manufacturing
Aug 10, 2026 · By Heraeus · 3D In-Depth, Manufacturing, Processes and Technology
Design View all
Siemens advances self-verifying agentic AI workflows for semiconductor and PCB design
Combines Siemens’ EDA expertise and software with NVIDIA AI infrastructure and software to improve result quality, time-to-results, tool-calling reliability and token efficiency for long-running engineering workloads Enables agentic AI workflows that help engineers improve productivity and design quality across the electronic design automation (EDA) lifecycle Delivers more predictable, trusted outcomes...
SPM Wafer Cleaning for Advanced Semiconductor Manufacturing
Wafer cleaning is one of the most critical steps in the semiconductor process flow, especially as dimensions continue to shrink to below the 1-nanometer (nm) node. Photoresist residue and particulates can reduce yields in large-die AI chips, impacting the performance of the final product or causing the chips to be scrapped. The sulfuric acid hydrogen peroxide step, or sulfuric peroxide mixture (SPM), is essential for removing organic contaminants from post-etch substrates and ion-implanted films, as well as for platinum silicide residue...
Devices View all
How Implantable Brain-Computer Interfaces Are Pushing the Boundaries of Precision Die Bonding
A patient who can no longer speak generates text directly from neural activity. A patient with paralysis controls a cursor using thought alone. Behind demonstrations like these is a difficult engineering problem: how do you assemble electronics delicate enough to interact with the human brain, while keeping them stable inside...
Navy’s Directed Energy Systems Integration Lab to Train Sailors on Laser Weapons
By Thomas McMahon Naval Surface Warfare Center, Port Hueneme Division, CA Sailors can now get certified in operating and maintaining the fleet’s most prevalent directed energy system through a new training program at Naval Surface Warfare Center, Port Hueneme Division (NSWC PHD)’s Directed Energy Systems Integration Laboratory (DESIL), with the first...
Latest Posts - Page 29
SUSS MicroTec Appoints New VP R&D
SUSS MicroTec has appointed Dr Rainer Knippelmeyer as VP R&D and CTO. In this function Rainer Knippelmeyer will oversee research...SEMATECH Completes Fully-integrated 300mm Line for Via-mid 3D ICs
In an ongoing effort to drive 3D IC integration, SEMATECH’s 3D Interconnect program has completed its 300mm 3D IC pilot...Lowering integration risks for 3D TSV products
A critical challenge for fabricating 3D products is the integration of the dies with through-silicon vias (TSVs) into functioning and...SEMATECH, SIA and SRC Team to Establish New Collaborative Program for Enabling 3D ICs
SEMATECH, the Semiconductor Industry Association (SIA), and Semiconductor Research Corporation (SRC) announced today they have established a new 3D Enablement...SPTS Opens New San Jose Facility At Silicon Valley Research Center
SPP Process Technology Systems (SPTS) announced the opening of its new facility in San Jose, CA, serving as the home...SEMICON West: Success for 3D –focused Companies
Is it mere co-incidence that companies who have invested in 3D technologies seem to have escaped the effects of the...Extending Legacy Technologies into the 3D Space
While TSVs technologies make their way out of R&D on to the manufacturing floor, improvements and developments in non-TSV 3D...EV Group Capitalizes MEMS Market Leadership, Further Diversifies Business with 3D IC and LED Manufacturing Technology Advances
Company to share key developments and highlights at SEMICON West
Alchimer Introduces Via Fill Technology
Alchimer S.A. has announced a groundbreaking advanced technology for filling narrow, high-aspect-ratio TSVs while significantly reducing...CMP/CMC/MOSIS partner to introduce a 3D-IC process
CMP/CMC/MOSIS announced a Grenoble-France based partnership for a 3D-IC multi-project wafer (MPW) service based on Tezzaron’s SuperContact technology and...
ECTC 2010 Panel Examines the Medical Device Market
Keith Cooper, Technology and Development, SET North America reports from ECTC 2010's Medical Device Market Panel, offering a view beyond...CEA-Leti and Docea Power to Combine Expertise on 3D Integration, Thermal and Low-power Design
French research insitute, CEA-Leti and Docea Power, developers of software for power and thermal analysis at the architectural level,...
CEA-Leti and SPTS to Collaborate On Next-Generation TSV Development
CEA-Leti and SPP Process Technology Systems (SPTS) have agreed to develop advanced 300mm through-silicon via (TSV) 3D-IC processes at CEA-Leti’s...EV Group Introduces New EVG610 Mask and Bond Aligner Optimized for Greater Cost and Process Flexibility
New System Provides World-class Alignment Technology at an Affordable Cost
Wafer-Level Camera Manufacturer, Nemotek Technologie, selects EV Group’s Solutions for Capacity Ramp
Follow-on Order Demonstrates the Strength of EVG’s High-volume Manufacturing Solutions for Wafer-level Camera ApplicationsNew Realities for TSV Processing
In this article, published in the May/June 2010 issue of Chip Scale Review Magazine,...SEMICON Singapore program features 3D InCites Partners
SEMICON Singapore gets underway next week (May 19-21), and the 3D track speaker line-up features...SEMICON West to address critical trends in 3D IC and Advanced Packaging
The SEMICON West 2010 show at Moscone Center in San Francisco, from July 13-15, will present a full program of...Who Invented the Through Silicon Via (TSV) and When?
In this post written and submitted by John H. Lau, Electronics & Optoelectronics Laboratory, ITRI, the true inventor of...