EDA Tools

EDPS 2017: NOT the usual Electronic DESIGN Process Symposium

EDPS 2017: NOT the usual Electronic DESIGN Process Symposium

When planning the 24th EDPS, the organizing committee, chaired by Shishpal Rawat, former Intel executive, took a number of bold steps EDPS was traditionally held in the spring. We moved EDPS to the fall because that’s a time when more new IC projects are being planned. After many years of holding it in Monterey, we moved EDPS to Milpitas to make it more easily accessible for Silicon Valley folks... »

Top Ten Reasons to Attend the 2017 European 3D Summit

Top Ten Reasons to Attend the 2017 European 3D Summit

It’s that time of year again! For the 5th consecutive year, SEMI Europe is hosting the European 3D Summit (formerly known as the 3D TSV Summit for editions 1-3), and it’s shaping up to be a stellar event. If you are still wavering about attending, here are 3D InCites’ top ten reasons to attend: 10: The opportunity to visit beautiful Grenoble, and taste the local fare with your industry colle... »

Advanced Packaging Challenges and Opportunities for 2015

Advanced Packaging Challenges and Opportunities for 2015

Our industry is seeing greater diversification in manufacturing processes than it has since its earliest days. In the front-end numerous new materials, architectures, and processes are under development to enable the continuing march toward smaller device sizes. In the back-end, and many places in between, advanced packaging processes and 3D integration are adapting processes from the front-end, v... »

Next-Gen MEMS Simulation Tool Makes Life Easier for ASIC Designers

Next-Gen MEMS Simulation Tool Makes Life Easier for ASIC Designers

I don’t usually write about MEMS. But every once in a while, when MEMS (stands for micro-electromechanical systems) touches anything to do with 3D integration, usually at the system-level, I might veer slightly out of my comfort zone to interview a MEMS supplier about their latest developments. I find it’s a good way to learn about the synergies and to cross-pollinate information. Today wa... »

Are Design Tools and Thermal Solutions the Missing Links to 2.5D and 3D IC Production?

Are Design Tools and Thermal Solutions the Missing Links to 2.5D and 3D IC Production?

On one side of the fence, we have semiconductor device manufacturers (fabs, foundries, and OSATS) claiming to be ready to ramp 2.5D and 3D IC devices to production, saying that remaining issues can be engineered out. On the other side, we have system integrators who, while they believe 2.5D and 3D ICs are the answer to their performance and power prayers, aren’t ready to dive in head first becau... »

3D Workshop Panel Discussion Focuses on 3D Standards and EDA Tool Readiness

3D Workshop Panel Discussion Focuses on 3D Standards and EDA Tool Readiness

 Are slow standardization and CAD-tool development hindering the progress of 3D IC design and integration? This was the topic of discussion during the Friday 3D Workshop at DATE 2014, which took place this year in Dresden, March 28, 2014. I was invited to moderate this panel discussion, which featured panelists from EDA suppliers, industry, and academia. We wanted to mix it up a bit and involve ... »

Making Progress with 3D IC Design and Test

Making Progress with 3D IC Design and Test

Thank you, Ann Steffora Mutschler (Semiconductor Engineering) for getting to the bottom of the difference of EDA tools for  2.5D and 3D IC design and test, and providing such a clear explanation in your post, “Evolution vs. Revolution”. In this 2-part post, Mutschler explores the EDA vendor arguments that “tool and design flow changes need to be evolutionary, rather than revolutionary.” A... »

3D IC Design: Outlook for 2014

3D IC Design: Outlook for 2014

To date we at Mentor Graphics have seen a handful of 3D IC design releases, and even more customer evaluations. However, the predominant driver seems to be a desire to understand the space in case their company elects to move into the space. In general, the perception seems to be that the costs for the current offerings are higher than expected. Moreover, many companies are still trying to determi... »

Part 2: 3D NAND Flash: Towering Spires or Costly Canyons?

Part 2: 3D NAND Flash: Towering Spires or Costly Canyons?

In my last blog posting I went over the cost aspects of the Samsung-Toshiba 3D NAND approaches. The conclusion is quite stark: if those vertical holes and trenches are more than a few tenths of a degree from the vertical, then the whole approach can be undercut in cost by more lithography-intensive layered approaches. At the risk of belaboring that point, see the IEEE paper published this month. N... »

And a Good Time was had by All – 3D InCites Awards Breakfast, 2013

And a Good Time was had by All – 3D InCites Awards Breakfast, 2013

Despite the chilly San Francisco morning temperatures, a sizable crowd of 2.5D and 3D enthusiasts gathered at the Impress Lounge to witness the inaugural 3D InCites Awards Breakfast, held July 11, 2013 during SEMICON West. For me, it was especially significant as it marked four years since I first launched 3D InCites at SEMICON West 2009. I felt truly honored to be surrounded by such industry elit... »

Page 1 of 3123