For EPYC, AMD partitioned the design to put the CPU functions that would benefit most from the next node (7nm) while leaving analog and I/O blocks for a less advanced technology. It all makes perfect sense. The analog circuits simply do not benefit from scaling transistors or interconnect pitches. It is even more striking to consider the I/O themselves with bump pitches for getting signals off chip scaling very slowly compared to the digital circuits. AMD calculated an additional 10% of silicon real estate required for the die-to-die communication blocks, redundant logic and other unnamed add-ons to enable the chiplet design compared to a hypothetical monolithic EPYC chip. The total die cost of the multiple chiplets saved 41% compared to AMD internal estimates for the monolithic processor.