Thinning wafers reduces the cost and technical difficulty of etching through-silicon vias (TSVs) in advanced “3D” packaging schemes. This has been the focus of a joint development project between imec, SPTS and other partners in order to optimize a “TSV-last” route for a multi-wafer stack using dielectric bonding and TSV interconnections.
Artificial intelligence, machine learning, even crypto currency mining is creating demand for High Performance Computing (HPC). Large interposers carrying GDU and 3D stacked memory cubes are starting to appear in server farms. For future stacked memories, workers are imagining how 32 or 64 memory wafers can be stacked together without breaking rules on stack height. Working with imec, SPTS has developed a Si thinning process to controllably thin the bulk Si to just 5um.
Thinning a whole wafer by dry plasma etching alone would be very slow and expensive, so this project opted to remove the majority of the silicon by more cost-effective grinding down to 50µm. The surface is then smoothed by chemical mechanical polishing (CMP) which removes only around 1µm of silicon, prior to a plasma-based blanket silicon etch to complete the thinning to the desired final thickness of around 5µm. The thickness of the thinned wafer must be uniform across the whole wafer to ensure the subsequent dielectric bonding and TSV formation steps are successful.
The joint project has demonstrated an optimized manufacturing route to thin, bond and connect up to 4 wafers, which eliminates the majority of the CMP processing resulting in a cost saving of around 50%. SPTS’s Rapier XE silicon etch system was used in this project offering a high silicon etch rate >9µm/min and the ability to tune out the enhanced etching that naturally occurs at the wafer edge. A new end-point solution was also developed to control the plasma processing during the final stages of the thinning.
 “Extreme wafer thinning optimization for via-last applications”, A. Jourdain et al., IEEE International Conference on 3D System Integration - 3DIC, San Francisco, CA, 2016