3D In Context

About Herb Reiter

After more than 20 years in technical and business roles at semiconductor and EDA companies, Herb Reiter founded eda2asic Consulting, Inc. in 2002 to focus on increasing the cooperation between EDA suppliers and ASIC vendors. In this role Herb introduced innovative IC design tools to the major semiconductor vendors worldwide. In 2008 he expanded his scope into Multi-die ICs. As chair of the GSA’s 3D-IC Working Group (2008-2011) and as SEMATECH business development consultant (2012 + ‘13), he broadened his horizon to include interposers and 3D-ICs technology, semiconductor materials as well as manufacturing, metrology and test equipment. In 2014 + '15 Herb consulted with Si2, to encourage development and standardization of data exchange formats for Interposer and 3D-IC design flows. Since early 2016 he is consulting with the newly formed Electronic System Design Alliance (formerly EDAC), to accelerate market acceptance of Multi-die ICs, the essential building blocks for the emerging System Scaling methodology.
Herb attended 40+ Continuing Education courses at Stanford University, earned an MBA at San Jose State University and Master Degrees in Business and Electrical Engineering at the University and the Technical College in Linz/Austria, respectively. He can be reached at herb@eda2asic.com

Here are my most recent posts

Breaking Down Walls between Board, Package, and IC Design Steps

Breaking Down Walls between Board, Package, and IC Design Steps

Many years ago, when I started in the semiconductor business, the circuit designers only had to worry about functionality and, after completing their job, “threw the design over the wall” to the layout team or contractor. As recently as 10 years ago, IC designers only had to worry about silicon performance and after verifying functionality and timing, they “threw the design over the wall” ... »

Book Review: Design and Modeling for 3D ICs and Interposers

Book Review: Design and Modeling for 3D ICs and Interposers

For almost 50 years the semiconductor industry has practiced continued shrinking of transistor feature sizes and has been able to pack, with every new process generation, more functionality, at lower cost, onto a single piece of silicon in one IC package. However, physical limits to shrinking and rapidly increasing cost of this methodology have triggered the development of alternatives that combin... »

READY – AIM – FIRE! Predictions for 2.5D ICs in 2014

READY – AIM – FIRE! Predictions for 2.5D ICs in 2014

Major SoC vendors, like Intel and IBM, started development work on 3D ICs more than a decade ago, but so far, economics have discouraged them from starting volume production. Ho-Ming Tong, CTO, ASE, and his team realized a few years ago that vertical stacking of logic die and/or heterogeneous functions did (and still do) require major engineering efforts and significant business model changes befo... »

IWLPC 2013

Thoughts on 2.5D and 3D IC Progress, as Presented at IWLPC 2013

The 10th International Wafer-level Packaging Conference (IWLPC 2013) was held at the DoubleTree Hotel in San Jose this week. I had an opportunity to attend part of the technical sessions and the keynote Invensas’ president, Simon Mc Elrea, presented on Thursday morning. I also enjoyed the 3D Panel, moderated by Sitaram Arkalgud, formerly at SEMATECH, now at Invensas, on Thursday afternoon. If yo... »


Comparing Samsung’s 3D NAND with Traditional 3D ICs

At last week’s Memcon 2013, which took place Tuesday, August 6, 2013, at the Santa Clara Convention Center, Keynoter Bob Brennen, Senior VP at Samsung, talked about the need for New DRAM and Flash Memory architectures. Richard Goering summarized Brennan’s keynote very well in his blog post. Because Brennan’s responsibility is to manage Samsung’s System Architecture Labs, he talked ... »

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