After 25 years, IRSP 2019 (former “Stress workshop”) is coming back to Silicon Valley, held at San Jose State University on November 4-6.
This meeting, in addition to traditionally covered stress and thermal issues at the level of materials and devices, will be dealing with reliability & performance problems at higher levels – circuits, chips, products. The focus will be the stress and thermal effects in advanced packaging, heterogeneous integration, and chip-package interaction. This year conference will provide a forum for direct interaction between experts from the field of materials/device reliability and from the design-for-reliability community addressing the same problems.
The event has a call for papers. Additionally, the schedule and speakers have been announced. Keynotes speech topics include “Effects of Scaling and Stress on Electromigration of Nanointerconnects and Future Perspectives” and “Reliability and Robustness in the Fully Connected World”.
Registration is open here. Early registration pricing ends September 3.
