The Truth About Moore’s Law is Revealed at 3D ASIP 2017

I’ve long held the belief that when it comes to reading scholarly works, very few people read the entire paper. At best, they read the title, introduction, and conclusion. At most, they skim the rest. Last week at 3D ASIP 2017, my suspicions were confirmed, when it was revealed by Dan Green, DARPA, that if the powers that be had bothered reading to the top of Page 3 of Gordon Moore’s “Cramming More Components onto Integrated Circuits”, the document that inspired Moore’s Law, we would have saved a lot of time, expense and effort trying to scale to smaller nodes. Why? Because they would have come to this paragraph:

“It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected. The availability of large functions, combined with functional design and construction, should allow the manufacturer of large systems to design and construct a considerable variety of equipment both rapidly and economically.”

That’s right. According to Green, heterogeneous integration was part of Gordon’ Moore’s master plan THE WHOLE TIME. No need to worry about the end, or changing the name to More than Moore.

In all seriousness, as Green explained to me further – it didn’t make sense to move from CMOS scaling to advanced packaging and heterogeneous integration solutions until we reached the inflection point where it no longer makes economic or performance sense to continue scaling monolithically. We officially reached that point with the publication of the last ITRS Roadmap in 2015. However, many argue that we reached that point in the early 2000’s when strained Si was introduced to achieve 90nm, then again at 45nm, when new materials were introduced, and then again at 22nm when TriGate transistors maintained scaling.

Green, whose talk focused on DARPA’S CHIPS Program (which stands for Common Heterogeneous Integration and IP Reuse Strategies), was one of several keynote speakers featured during the 14^th Annual 3D ASIP Conference, which took place December 5-7 2017, in Burlingame CA. In its second year under the IMAPS banner, the conference has evolved considerably over the years from when 3D integration was an emerging concept, to now when it joins the ranks of mainstream heterogeneous integration technologies. Indeed, the conference was originally named 3D Architectures for Semiconductor Integration and Packaging (3D ASIP) and is now officially titled 3D Architectures for Heterogeneous Integration and Packaging. (3D AHIP just doesn’t roll off the tongue quite the same as 3D ASIP though, does it?)

Back in those early days, 3D TSVs were riding the hype cycle, and everyone wanted to play with the cool 3D kids on the block (Mitsumasa Koyanagi, Bob Patti, Peter Ramm, Phil Garrou, Eric Beyne, Juergen Wolf, John Lau, Gilles Poupon, James Liu, Paul Franzon and others). Early programs focused on the process and technology developments, later editions took a business development spin in search of the “killer application.” This year, the focus returned to technology development, and there was a lot less discussion about application drivers. For the past two years, the event has had a more intimate feel; an annual gathering of hard-core 3D and advanced packaging veterans who’ve come together to share their knowledge.

The big story this year was DARPA’s CHIPS program, with Green’s keynote and an entire session devoted to it. The subplots featured frequently discussed hot topics like hybrid bonding, aka DBI®, and all the 3D integration it will enable; the importance of package design kits, and of course, the latest on fan-out wafer level packaging.

Calling 2017 a breakout year, Prior said that EUV lithography is on the cusp of production. Memory has experienced enormous growth that he says will continue through 2018 until price erosion comes into play. We’ve reached volumes in 2.5D and 3D technologies, and organic LEDs (OLEDs) are finally coming to the mainstream. While Moore’s law isn’t over, there’s lots more spending taking place to enable next node progression. “Packaging technology is a key part of what will enable further innovation,” he said, noting that investment in packaging has increased substantially for companies to remain competitive. He expects the 2.5D and 3D TSV domain to account for 15% of the advanced packaging value-added through 2021 to the tune of $1B.

Jim Walker, WLP Concepts, said the industry-wide paradigm shift away from SoC scaling to heterogeneous integration is because design costs for system-on-chip are too high for many internet-of-things (IoT) applications. Advanced packaging has lower non-recurring engineering (NRE) costs than Si integration. He talked about different business model scenarios based on what Walker called “vertical integration on an outsourcing basis.” Walker says the ultimate question going forward, will be who has the wafer and where are the value-added steps going to wind up?

Enter Chiplet Integration
Reducing NRE is one of the key advantages of the CHIPS program, which focuses on the development of “design tools, integration standards, and IP blocks required to demonstrate modular electronic systems that can leverage the best of Department of Defense (DoD) and commercial designs and technology,” explained Green (details here). The concept involves disaggregation of systems-on-chip (SoC) designs into functional, verified, reusable, physical IP blocks of circuitry that are reintegrated on a substrate. The focus is on modular IP, not new IP. This should not be confused with system-in-packaging (SiP) approaches, which involves integrating entire chips. These components are called “chiplets” or “dielets” depending on who you’re talking to. The chiplet concept reduces NRE Cost by 4X, noted Northrup Grummond’s Pavel Borodulin. (It’s important to note that while UCLA’s CHIPS program, spearheaded by Subu Iyer, is on a similar quest, it is a separate entity. In this case, the acronym stands for the Center for Heterogeneous Integration and Performance Scaling. You can read more about it here.)

Northrup Grummond’s DAHI (Diverse Approach Heterogeneous Integration) program is part of DARPA’s CHIPS initiative, and as Augusto Gutierrez-Aitken explained, involves integrating functional compound semiconductor chiplets onto CMOS using heterogeneous integration interconnect technologies. Gutierrez-Aitken noted they have created a process design kits using Cadence tools for this approach, and have also focused efforts on finding solutions to thermal challenges, resulting in a tool called DAHI Compact Analytical Thermal Solver (DAHI CAT).

The chiplet integration concept is also catching on at Intel, noted Sergey Shumarayev. Because of increased complexity, system latency, and power, combined with a high NRE and longer time to market, the company has started looking at high-density packaging to enable heterogeneous integration. The Intel Stratix 10 uses Intel’s embedded multi-die interconnect bridge (EMIB) to interconnect high bandwidth memory (HBM) chiplets, FPGA chiplets, transceiver chiplets, etc; to mix process node and system functions in a single device. The company is also realizing the value of partnership, most recently working with long-time rival AMD to take on Nvidia’s gaming market share with 8th Gen Intel Core family. Here again, EMIB is the star, used to integrate HBM2 with an Intel processor and an AMD graphics unit.

“Is there any one company that has a monopoly on innovation?” asked Shumarayev. “Heterogeneous integration allows you to innovate with the whole world. A monolithic approach assumes that one company has a monopoly on innovation.” Indeed.

If the presentations at  3DASIP 2017, IMAPS 2017 and IWLPC 2017 are anything to go by, I expect we will hear lots more about this chiplet integration over the next few years. And yes, I did just coin a new phrase. It’s a lot more concise than heterogeneous integration, isn’t it? Just remember, you heard it here first. ~ FvT