Processes and Technology

Mentor Graphics: Tessent MemoryBIST

Product Description Tessent Memory BIST (built-in self-test) allows you to test and diagnose failures in memory die and in the through-silicon-via (TSV) connections between the memory and logic die within a stacked package. This solution supports any memory stacking configurations without any change to the test infrastructure Testimonial The Tessent...

3D stack courtesy of DARPA

Activity Heats up for 3D IC Chip Cooling

3D ICs have clearly caught the eye of the military and aerospace electronics industries. I came across two separate announcements – one from Georgia Institute of Technology and one from IBM Microelectronics – that each had been awarded DARPA grants to work on chip-level cooling technologies as part of the...

Talking Points: Interconnectology, Inspiring a Paradigm Shift

At the BiTS Workshop 2013, the talk show segment, Talking Points, examined the concept of Interconnectology and how adopting new terminology can inspire a paradigm shift in the design and development of next-generation interconnect technologies, thereby impacting the semiconductor device manufacturing value chain. Hosted by Françoise von Trapp, 3D InCites,...

3D IC Blogosphere Update – Feb 22

Has it really been a month since the European 3D TSV Summit? This inaugural event certainly caused a buzz in the blogosphere! In addition to all my coverage after having attended the event, Phil Garrou has been slogging his way thorough the proceedings to provide an in-depth review on Insights...

2013 Predictions for 3D ICs as told by Everyone – Part 1

It’s that time of year again when various electronics trade publications invite industry executives to peer into their crystal balls and make their predictions for the coming year. I’ve been perusing through everything from overall industry forecasts by market analysts to suppliers eager to promote their core competencies for 3D...

MonolithIC 3D's PDN concept f removing heat from 3D ICs.

Tying up 2012 3D IC Loose Ends

I don’t know about you, but I always find that amidst the holiday hubbub, the really important stuff gets shoved aside and falls through the cracks. Just in case you missed them, here are some good 3D related posts that may have been lost in the December race to “get...

ACM Research team at 3D ASIP 2012.

ACM Research: New Kid on the 3D Block

Yesterday at the pre-conference symposium for 3D Architectures for Semiconductor Integration and Packaging (3D ASIP), I was fortunate to get an up close and personal tutorial preview by David Wang, CEO of ACM Research, on the tool manufacturer’s latest process solution for two critical points in the TSV fabrication process. The...

3D Company Updates

There are a couple of notable updates circulating this week involving companies in the 3D space. The first I saw was news from Sony that it has introduced its next-generation CMOS Image sensor they claim is “ the industry’s smallest, CMOS image sensor and camera system”. The image sensor is...

3D TSVs: Will Europe Lead the Way?

The first European 3D TSV Summit (January 22-23, 2013) hasn’t even happened yet, and already its intended message is becoming clear: Europe is ready to tackle those remaining issues and lead the world down the home stretch. It makes sense, since Europe’s R&D centers (imec, CEA Leti, Fraunhofer IZM) has...

Multi-Die Integration Provides Multifaceted Solutions

Multi-Die Integration Provides Multifaceted Solutions By Francoise von Trapp, 3D InCites  This year’s Roadmaps for Multi-Die Integration Symposium, hosted by MEPTEC on November 14, 2012 at the Biltmore Hotel in Santa Clara, CA, offered some interesting and different perspectives than the garden-variety 2.5D and 3D IC conferences of late. While...

What 3D Means in eWLB

Last week (November 6) STATS ChipPAC issued a press release announcing that its advanced eWLB provides a platform for 2.5D and 3D technologies.  In search of further information about this, I found a feature article recently published in Solid State Technology that explained how eWLB can be leveraged for 2.5D and...

3D Technology Features in Review

The latest digital issues of Chip Scale Review and  iMicronews’ 3D Packaging magazines hit the virtual “stands” last week, and perhaps in honor if the 3D ASIP Conference that gets underway later this week, there are some hot new 3D technologies being featured. But first, to bring everyone up to...