3D Topics

Samsung’s 3D V-NAND Flash Product – The Spires of El Dorado?

Finally! After a year’s worth of guesswork, Samsung’s 3D V-NAND Flash cell has been revealed. Thanks to the expertise of Chipworks we can see how the memory array looks in the 86 Gbit 32-layer 2nd generation V-NAND. Figure 1 shows Chipworks’ beautiful cross section. My intention here is to explain the structure,...

Low-Temp, Ultra-Fine-Pitch Cu Interconnections for Manufacturable, Solder-free Assembly

A novel copper interconnection technology is being pioneered by Georgia Tech’s Packaging Research Center (GT-PRC) to achieve manufacturable solder-free assembly at low temperatures. By interfacing engineering and process design, the Cu interconnections are shown to meet both thermal cycling and ultra-high current-handling needs. This technology is now being applied to mobile...

TSV MEOL Process Flow for Mobile 3D IC Stacking

Moore’s law is approaching physical limitations of CMOS scaling, and three dimensional (3D) integration technologies have been proposed as solutions. Wide band transmission between logic and memory is becoming indispensable for not only mobile products, but also other products related to network systems such as servers and data centers. These...

Are there still Gaps in 3D IC Readiness?

Good news! At last week’s GSA 3D IC Packaging Working Group Meeting, July 23, 2014, Jan Vardaman uttered the words I’ve been waiting to hear her say for quite some time. “Memory stacks with TSVs are here!” Vardaman cited three companies actively involved in new memory architectures, all of which...

GlobalFoundries and IBM: Stuck on the Rumor Mill?

There’s nothing like a little industry gossip to get the juices flowing. I love it when the media churns out news articles based purely on speculation, quoting individuals who request anonymity, and publishing the names and titles of those who refuse to comment on speculation. No doubt you’ve all seen...

Semiconductor Equipment Manufacturer Consolidation Update

It was a much-talked-about topic this year at SEMICON West 2014 (SW2014) – this trend of semiconductor equipment manufacturer consolidation. Just in the past year, we’ve read the headlines about Applied Materials (AMAT) and Tokyo Electron ‘s (TEL) impending merger; LTX Credence’s acquisition of Multitest, Everett Charles, Technologies and atg...

The Internet of Things and Semiconductor Test

Herb Reiter, eda2asic, presented this poster presentation titled “The Internet of Things and Semiconductor Test” at the Test Vision 2020 Workshop during Semicon West 2014. Here is the printed transcript of the talk. The accompanying slides referenced in the text can be downloaded as well. In the 1990s cell phones...

Does 3D Integration Need to Go to HVM To be Real?

Consider for a moment that the ultimate goal of 3D integration is not to achieve high volume manufacturing (HVM) in high bandwidth memory and logic applications for mobile devices, but rather to be an enabler for heterogeneous integration of disparate technologies for everything from medical and automotive applications to industrial...

Market Outlook for Permanent Wafer Bonding

Permanent wafer bonding can be categorized based on bonding with or without an intermediate layer. Intermediate layers can be subcategorized into insulating layers including glass frit bonding, adhesive bonding, or metallic bonding including Cu-Cu/oxide “hybrid” bonding, solder bonding, and thermo-compression copper-copper bonding as shown in Figure 1. MEMS devices are...

SEMICON West 2014: Are 3D ICs Getting the Squeeze?

With the continued innovations in packaging technologies and 2.5D interposers pushing 3D ICs further out from one end, and 16/14nm nodes already qualified without TSVs, making us wait until 10nm, are 3D ICs suddenly getting the squeeze from both sides? That’s one theory I took away from all the conversations...

Ye Antique Towers – Samsung’s 3D NAND Flash SSD 850 Pro

Samsung’s introduction of its 3D NAND Flash SSD 850 Pro has led to the inevitable hullabaloo. Amid all the fuss, it hasn’t taken long for someone to publish the actual die size. This of course is the golden nugget of information that lays the foundation for any cost analysis. Figure 1 shows...

Having the Courage to Design in 3D TSVs

I don’t know why it still surprises me to read conflicting reports on the progress of 3D TSVs. But I think Ron Huemoeller, Amkor, finally hit on it in his closing remarks during today’s webcast, “TSV Packaging at the Tipping Point”, moderated by Pete Singer, Solid StateTechnology/Extension Media. Huemoeller’s presentation and...

Path Finding: Who Performs and When?

Microelectronic products all have mechanical, thermal and electrical properties that degrade until the device is permanently damaged. Path finding adds value to an end-product by pre-determining where the breaking points are, and if or how they can be enlarged. For decades, product designers have used various methods of path finding...