Oct 01, 2014 · By Bill Martin · Blogs
TechSearch International’s recently published 3D IC Gap Analysis report has a section for a new class of tools called Path Finding, which are separated from the classical EDA tools. The classical EDA tools discuss implementation and verification for IC, package, and PCB. Path Finding tools are used well before the Implementation/Verification...Sep 30, 2014 · By Francoise von Trapp · Book Reviews
“From so simple a beginning endless forms most beautiful and most wonderful have been, and are being, evolved.” ~ Charles Darwin Charles Darwin was obviously not thinking of 3D semiconductor memories when he said this but the thought is appropriate. With the recent introduction of the first monolithic 3D Flash...Sep 26, 2014 · By Francoise von Trapp · 3D In-Depth
Earlier this year, I published an open letter to chip and system-level designers regarding 3D integration, suggesting they consider 3D integration technologies as a solution to dealing with the increasing complexity of SoC designs. The post was inspired by my attendance at the Design and Test Europe (DATE 2014) conference,...Sep 25, 2014 · By Jeff Calvert · Resource Library
3D integration has created a complex landscape of many different package architectures and integration approaches that have diverse materials needs and uncertain insertion timing. The multitude of processes required do not fit neatly into the established pigeonholes of front-end and back-end. Processes such as through silicon via (TSV) fabrication require...Sep 18, 2014 · By Francoise von Trapp · 3D In-Depth
It’s been a long time coming, but Kulicke & Soffa has seen the writing on the wall, and it reads: “2.5D and 3D IC assembly is a hot market.” Why else would the wire-bond giant invest in developing a thermocompression chip-to-substrate (C2S) bonder for high-volume 2.5D and 3D IC die...Sep 18, 2014 · By Francoise von Trapp · Blogs
Last week, I caught IC Insights’ Bill McClean’s talk at the IMAPS Arizona luncheon. In addition to predicting a steady growth trend for the semiconductor industry that will reach double digits by 2016, followed by a cyclical downturn to -1%in 2017, McClean also discussed some major trends he expects will...Sep 17, 2014 · By Jan Vardaman · 3D Event Coverage
I attended the 3D IC Technology Forum at SEMICON Taiwan 2014, where many of the discussions focused on the latest memory announcements in 3D ICs from Micron, SK Hynix, Samsung, and Tezzaron. While the world still waits for the introduction of a Wide I/O mobile DRAM and logic part, memory...Sep 15, 2014 · By Francoise von Trapp · 3D In-Depth
CMOS image sensors (CIS) have often been heralded as the first 3D devices in volume manufacturing. However, this is not really the case. Shellcase MVP, the first generation of CIS that used through silicon vias (TSVs) to form interconnects was still a 2D device. (Remember, TSV is not always synonymous with 3D)....Sep 12, 2014 · By Herb Reiter · 3D In Context
This week I had the privilege to attend my first Intel Developer Forum (IDF). Like many of us, I have become more energy-conscious, so took the train to get there and back. On my way back I didn’t have to concentrate on the traffic around me and had time to...Sep 09, 2014 · By Francoise von Trapp · 3D In-Depth
I don’t usually write about MEMS. But every once in a while, when MEMS (stands for micro-electromechanical systems) touches anything to do with 3D integration, usually at the system-level, I might veer slightly out of my comfort zone to interview a MEMS supplier about their latest developments. I find it’s...Sep 08, 2014 · By Francoise von Trapp · 3D Event Coverage
While at first glance, 3D integration technologies seem to be relegated to one two-hour session at this year’s SEMICON Europa, which takes place October 7-9, 2014 in Grenoble, France; in reality 3D integration is a pervasive technology that will be discussed in many different programs and sessions. To make it...Sep 04, 2014 · By Klaus Ruhmer · Resource Library
In recent years, 2.5D packaging has quickly gained acceptance as an advanced packaging process, and the first products using this technology are now coming to market.¹ Most estimates project growth for 2.5D interposer packaging faster than the industry as a whole. Similar to the multi-chip modules (MCMs) of the past,...Sep 03, 2014 · By Francoise von Trapp · Blogs
While 3D IC production is underway for memory devices, some say demand for 3D ICs is still years away. Could both be right, or are we getting mixed messages? Today’s news from SEMICON Taiwan, in which a DigiTimes reporter quoted Mike Liang, president of Amkor Technology Taiwan as saying that...Aug 27, 2014 · By Francoise von Trapp · Blogs
Year’s ago, when I was managing editor of Advanced Packaging Magazine, each January issue featured an industry forecast cover story. For several years in a row, that issue predicted advanced packaging would be the key to improved performance at lower power and lower cost. January of 2007, we declared “Packaging...Aug 26, 2014 · By Aric Shorey · Resource Library
Glass has many properties that make it an ideal substrate for interposers such as: ultra-high resistivity and low electrical loss, low dielectric constant, and adjustable coefficient of thermal expansion (CTE). Leveraging glass-forming processes such as Corning’s fusion forming process provides roughness < 0.5nm rms, and flat substrates with good stiffness....Aug 21, 2014 · By Herb Reiter · 3D In Context
Last week, HotChips 2014 (aka HC26) was held at the Flint Center within the De Anza College in Cupertino, California. As in many previous years, I attended both the Sunday tutorial and the main conference on Monday and Tuesday. As usual, there were great keynotes and lots of interesting technology news. The tutorial always focuses...Aug 19, 2014 · By Antun Peic · Resource Library
In Part 1 of this article series, we noted that despite the potential benefits associated with 3D and interposer-based 2.5D designs, the incorporation of TSVs poses significant challenges to the performance and reliability of 3D wafer level packages (3D WLP). Among these is the generation of TSV stress in 2.5D/3D...Aug 18, 2014 · By Antun Peic · Resource Library
As traditional semiconductor scaling becomes increasingly complex and cost-prohibitive, transitioning from planar chip packaging architectures to 2.5D/3D stacked die package architectures has become key to enable the integration of greater amounts of chip functionality in smaller form factors. This need for form factor reduction, together with smaller process geometries and...Aug 15, 2014 · By Francoise von Trapp · Blogs
Ever since SEMICON West 2014, I’ve been seeing a lot of coverage of the 2.5D and 3D adoption question on Semiconductor Engineering, an industry content platform that covers the spectrum of semiconductor topics, and occasionally covers 2.5D and 3D, providing the perspective of chip architects, engineers, end users, industry organizations...Aug 12, 2014 · By Andrew Walker · Blogs
Finally! After a year’s worth of guesswork, Samsung’s 3D V-NAND Flash cell has been revealed. Thanks to the expertise of Chipworks we can see how the memory array looks in the 86 Gbit 32-layer 2nd generation V-NAND. Figure 1 shows Chipworks’ beautiful cross section. My intention here is to explain the structure,...