3D Memory Using Conductive Lines for Vertical Interconnects

3D Memory Using Conductive Lines for Vertical Interconnects

The push for size reduction is reaching the segment of vertical interconnects. Current technology has a lower limit of approximately 0.150mm (0.006”) with pump and materials being the limiting factor. GPD Global through cooperation with MicroCoat Technologies have developed a process to dispense vertical interconnects at line widths from 0.075 to 0.100mm. A combination of fluid formulation and p... »

Image Courtesy of TSMC Ltd.

What Node Names Really Mean; The TB/DB Saga continues; HMC update

Did you know that when foundries talk about 14nm and 16nm node chips, these devices are in reality no denser than their 20nm predecessors? Or that a particular node name does not reflect the size of any particular chip feature, as it once did? Or that since 2007, the doubling of transistors on a chip has actually been more like 1.6x the number of the previous generation? According to a recent feat... »

Courtesy of Governor Cuomo's press office

Nano Utica gets $1.5B Infusion; Probably Good Die Revisited; Developments in Monolithic 3D

Word on the street is, New York will soon be known as Nano York, with all the money the state is pouring into nanotechnology research and development. The most recent announcement by Governor Cuomo is a $1.5 Billion Public-Private investment intended to turn the Mohawk Valley (Utica) into the next major hub for nanotechnology research. A consortium of global technology companies headquartered at t... »

courtesy of NORDSON Asymtek

Is it Time for Fluxless Processes for 3D Packaging?

A 3D InCites reader recently inquired whether cost drivers and fine-pitch requirements in 3D applications are moving manufacturers away from flux towards fluxless processes in the bumping steps for both bump formation and assembly.To answer this question, 3D InCites turned to the materials and equipment experts, speaking with Jeff Calvert, Global R&D Director, Advanced Packaging Technologies a... »

Dynaloy: A Formula for Cleans
CoatsClean Before CoatsClean - negative resist film coated bumped wafer. After - squeaky clean bumps!

Dynaloy: A Formula for Cleans

It’s hard to believe that inside such a non-descript building set back down a picturesque country lane in (almost) rural Indiana, really cool things are happening. This is the home of Dynaloy, LLC, a subsidiary of Eastman Chemical Company, where innovative chemical formulations are being developed to remove the most stubborn of photoresists and polymer residues left behind during semiconductor m... »

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