Manufacturing

Setting the Record Straight On Applied Materials’ PVD Tool for 3D TSVs
TSVscale Ventura

Setting the Record Straight On Applied Materials’ PVD Tool for 3D TSVs

Nothing makes me click a link faster than a title like “3D Chip Stack Tool Sends TSV Into High-Volume”, because who in this industry isn’t waiting for that precise moment when through silicon vias (TSVs) go into high volume manufacturing? Unfortunately, the EE Times story behind that provocative title was a little less than accurate, because as we all know, one tool introduction isn’t goin... »

2013 ITRS Roadmap Calls for 3D Power Scaling; Monolithic 3D Gains Traction
11235297_s

2013 ITRS Roadmap Calls for 3D Power Scaling; Monolithic 3D Gains Traction

At the beginning of April, the Semiconductor Industry Association released the 2013 International Roadmap for Semiconductors (ITRS), which has traditionally served as a guide for “assessing and improving the future of semiconductor technology,” according to Brian Toohey, president and CEO, Semiconductor Industry Association. Sponsored by five regions of the world including Europe, Japan, Korea... »

ASE and Inotera Memories to Offer Novel 2.5D Manufacturing Solutions

ASE and Inotera Memories to Offer Novel 2.5D Manufacturing Solutions

Last week, ASE and Inotera Memories announced they had entered into a joint development project (JDP) intended to both strengthen ASE’s system-in-package (SiP) capabilities and expand Inotera’s foundry services beyond its core competency of memory manufacturing to silicon interposers. The goal is to provide novel 2.5D manufacturing solutions. Prior to the companies’ official announcement, ru... »

SUSS MicroTec Launches Mask Aligner MA200 Gen3

SUSS MicroTec Launches Mask Aligner MA200 Gen3

Garching, April 2, 2014 – SUSS MicroTec, a global supplier of equipment and process solutions for the semiconductor industry and related markets, has launched the new Mask Aligner MA200 Gen3 today. The tool is designed for high-volume manufacturing and can be used for exposing wafers with a diameter of up to 200mm. This latest generation tool is a further development of the very successful MA200... »

Latest Developments in Cleans for TSVs and Cu Bumps
50micronbump

Latest Developments in Cleans for TSVs and Cu Bumps

At IMAPS DPC 2014, which took place March 11-13, 2014, in Fountain Hills, AZ, there were several presentations focused on new developments in cleans for TSVs and Cu bumps for 2.5D and 3D IC processes. Cleans has become increasingly important as bump pitches are reduced and TSVs have higher aspect ratios. It’s not just about being clean enough, but also about surface preparation for the next proc... »

Page 2 of 181234»