Devices

Lessons Learned From the Trenches of 3D IC Manufacturing for Sensor Applications
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Lessons Learned From the Trenches of 3D IC Manufacturing for Sensor Applications

The technologies are ready, the target high volume  applications for 3D IC manufacturing have been identified, and now it’s about convincing system architects there’s more to gain from designing in 2.5D and 3D ICs than there is to lose. At last week’s European 3D TSV Summit (January 21-22), two European manufacturers took to the podium to shared their reasons for implementing 2.5D and 3D in... »

3D NAND Flash – Towering Spires or Costly Canyons? – Part 4
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3D NAND Flash – Towering Spires or Costly Canyons? – Part 4

If you’ve followed me thus far in the three preceding posts, well done! We started by questioning the cost assumptions. Then we set the scene to be able to explain the vanishing string current problem, and then introduced the concept of pass disturb. In this post, as promised in the previous one, I want to deal with pass disturb in more detail, which is one of the more important reliability chal... »

Part 2: 3D NAND Flash: Towering Spires or Costly Canyons?
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Part 2: 3D NAND Flash: Towering Spires or Costly Canyons?

In my last blog posting I went over the cost aspects of the Samsung-Toshiba 3D NAND approaches. The conclusion is quite stark: if those vertical holes and trenches are more than a few tenths of a degree from the vertical, then the whole approach can be undercut in cost by more lithography-intensive layered approaches. At the risk of belaboring that point, see the IEEE paper published this month. N... »

Internet of Things

Friday’s Blog is brought to you by the Internet of Things

The Internet of Things, or “IoT” certainly seems to be the social media buzz phrase of the week. It seems every link I clicked on today took me to a post discussing the IoT. You can blame the flurry of technical blog coverage on recent events like the Trillion Sensors Summit, ARM TechCon 2013, CIsco’s Internet of Things World Forum, and Intel’s IDF 2013. All at once, Cisco Systems, Fai... »

Image Courtesy of TSMC Ltd.

What Node Names Really Mean; The TB/DB Saga continues; HMC update

Did you know that when foundries talk about 14nm and 16nm node chips, these devices are in reality no denser than their 20nm predecessors? Or that a particular node name does not reflect the size of any particular chip feature, as it once did? Or that since 2007, the doubling of transistors on a chip has actually been more like 1.6x the number of the previous generation? According to a recent feat... »

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