Design

3D Integration Workshop Faces Reliability Challenges Head On
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3D Integration Workshop Faces Reliability Challenges Head On

The Friday 3D Integration Workshop at DATE 2014 once again found me among friends, as an intimate group of about 30 gathered to spend a day sharing knowledge gained since last year’s workshop. My key take-away for the day was how to achieve reliability and robustness. Jürgen Wolf, director of the Fraunhofer IZM-ASSID 3D integration program stepped in as keynote speaker to replace Yole Développ... »

Making Progress with 3D IC Design and Test

Making Progress with 3D IC Design and Test

Thank you, Ann Steffora Mutschler (Semiconductor Engineering) for getting to the bottom of the difference of EDA tools for  2.5D and 3D IC design and test, and providing such a clear explanation in your post, “Evolution vs. Revolution”. In this 2-part post, Mutschler explores the EDA vendor arguments that “tool and design flow changes need to be evolutionary, rather than revolutionary.” A... »

3D IC Design: Outlook for 2014

3D IC Design: Outlook for 2014

To date we at Mentor Graphics have seen a handful of 3D IC design releases, and even more customer evaluations. However, the predominant driver seems to be a desire to understand the space in case their company elects to move into the space. In general, the perception seems to be that the costs for the current offerings are higher than expected. Moreover, many companies are still trying to determi... »

2.5D Interposer Innovations from Silex and eSilicon
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2.5D Interposer Innovations from Silex and eSilicon

2.5D interposers sparked a good amount of discussion at this year’s 3D ASIP conference (December 11-13, 2013, Burlingame CA), with a session devoted to “Interposers for all of Us” and other presentations scattered throughout the program to address such issues as thin wafer handling, and heterogeneous integration. Weighing in on Si interposer innovations was Peter Himes, of Silex, who talked ... »

Part 2: 3D NAND Flash: Towering Spires or Costly Canyons?
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Part 2: 3D NAND Flash: Towering Spires or Costly Canyons?

In my last blog posting I went over the cost aspects of the Samsung-Toshiba 3D NAND approaches. The conclusion is quite stark: if those vertical holes and trenches are more than a few tenths of a degree from the vertical, then the whole approach can be undercut in cost by more lithography-intensive layered approaches. At the risk of belaboring that point, see the IEEE paper published this month. N... »

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