Written by and for the design community, 3D by Design features thought leaders who understand the benefits of designing in 3D and have been instrumental in the commercialization of 3D integration technologies.

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Highlights from HotChips 2014: 21 HBM Design-ins Ongoing!

Last week, HotChips 2014 (aka HC26) was held at the Flint Center within the De Anza College in Cupertino, California. As in many previous years, I attended both the Sunday tutorial and the main conference on Monday and Tuesday. As usual, there were great keynotes and lots of interesting technology news. The tutorial always focuses on an important technology or market trend. This year was no e... »

Are Chip Architects Finally Climbing on the 2.5D and 3D Bandwagon?

Ever since SEMICON West 2014, I’ve been seeing a lot of coverage of the 2.5D and 3D adoption question on Semiconductor Engineering, an industry content platform that covers the spectrum of semiconductor topics, and occasionally covers 2.5D and 3D, providing the perspective of chip architects, engineers, end users, industry organizations and standards bodies. What I find most interesting in these... »

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Are there still Gaps in 3D IC Readiness?

Good news! At last week’s GSA 3D IC Packaging Working Group Meeting, July 23, 2014, Jan Vardaman uttered the words I’ve been waiting to hear her say for quite some time. “Memory stacks with TSVs are here!” Vardaman cited three companies actively involved in new memory architectures, all of which involve stacking memory either with or without interposers – Tezzaron, Micron and Hynix. She ... »

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Having the Courage to Design in 3D TSVs

I don’t know why it still surprises me to read conflicting reports on the progress of 3D TSVs. But I think Ron Huemoeller, Amkor, finally hit on it in his closing remarks during today’s webcast, “TSV Packaging at the Tipping Point”, moderated by Pete Singer, Solid StateTechnology/Extension Media. Huemoeller’s presentation and that of David Butler, SPTS, once again reinforced wha... »

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Should EDA vendors, OSATS, and their customers cooperate more?

Last week, I attended the packaging-focused 64th Electronic Components and Technology Conference (ECTC) 2014 in Orlando. This week I spent three days at the EDA-focused 51st Design Automation Conference in San Francisco. In addition to realizing that these two locations are about three thousand miles apart, I noticed that the packaging and EDA camps are still far apart in regards to share of mind ... »

An Open Letter to Chip and System-level Designers Regarding 3D Integration

Dear Chip and System-level Designers, Allow me to introduce myself. My name is Françoise von Trapp, and I am known in the semiconductor industry as “The Queen of 3D”. This is because I have held a deep interest in 3D integration technologies, and have devoted the past 7+ years to following the development of the processes involved from proof of concept through to manufacturability, and report... »

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Calling for A Collaborative Semiconductor Supply Chain Comes at DATE 2014

Design and Test Europe 2014 (DATE 2014), which took place in Dresden, March 24-28 2014, brought together semiconductor design and test engineers from all over Europe and around the world for the purpose of understanding the latest trends, methodologies, and technologies being developed to address the ever-changing needs of chip design and test for the semiconductor and microelectronics industry. ... »


Breaking Down Walls between Board, Package, and IC Design Steps

Many years ago, when I started in the semiconductor business, the circuit designers only had to worry about functionality and, after completing their job, “threw the design over the wall” to the layout team or contractor. As recently as 10 years ago, IC designers only had to worry about silicon performance and after verifying functionality and timing, they “threw the design over the wall” ... »

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