As we mentioned in IFTLE 537, IMAPS held the Onshoring: Packaging and Assembly Workshop prior to the traditional IMAPS fall symposium. Let’s take a look at what we learned from some of those key presentations. And then we’ll look at an important announcement by TSMC about its 3DFabric Alliance.

Intel Awarded Phase 2 of the SHIP Program

Figure 1: The DoD awards Intel participation in phase 2 of its SHIP Program.

Figure 1: The DoD awards Intel participation in Phase 2 of its SHIP Program.

John Sotir discussed “Advanced Packaging Capabilities at Intel” with the main message being that Intel continues to scale its Advanced Packaging Technologies Roadmap. With the focus of this workshop being onshoring advanced packaging, Intel also made clear that participation in multiple programs such as SHIP has allowed Intel to drive design and prototype diverse configurations for the U.S. Government and the Defense Industrial Base (DIB).

The DoD is especially eager to access the following Intel advanced packaging solutions.

Figure 2: Intel’s advanced packaging solutions are on the DoD radar. (Source: Intel)

Intel remains focused on:

Figure 3: Intel’s state-of-the-art technology. (Source: Intel)

They offered the following as an example of reuse and standardization strategies being used to manufacture various multichip packages.

Figures 4 & 5: Potential MCP reuse pathways. (Source: Intel)

Quorvo’s SHIP Program

Qorvo is running its SHIP program out of its Richardson TX facility.

The company is focusing on three main areas:

  • SHIP-RF DC (Design Center)
  • SHIP-RF ATC (Assembly and Test Center)
  • Advanced technology development – rigid interposer/embedded die

SHIP Design Center will be the focal point where customers will:

  1. Access design simulation, verification, and layout tool kits for design at their facilities
  2. Collaborate and/or co-design with project partners, including Qorvo
  3. Architect next-generation System in Package (SiP) platforms using SHIP DC IP Block Libraries
  4. Design and verify circuit and layout using an integrated mixed signal EDA platform
  5. Validate SiP prototypes using SHIP DC multichannel and mixed-signal test systems
  6. Project manage programs with advanced life cycle management tools

Qorvo’s roadmap for onshore capability is shown in Figure 6.

Figure 6: Qorvo’s onshore roadmap (Source: Qorvo)

New and expanded capability includes:

  • High-speed / fine-pitch flip chip lines
  • Die attach (vacuum reflow & sintered)
  • Mold – transfer
  • Mold compression

Figure 7: Embedded glass interposer with TSVs (source: GaTech PRC)

  • Package thinning
  • Laser ablation
  • Wafer-level packaging
  • Automated inspection
  • Ball mount
  • EMI shielding

In terms of advanced technology development, Qorvo is focused on developing an embedded glass interposer advanced packaging solution with through glass vias (TGVs) as shown in Figure 7. The company is working with the onshore capability to deliver such embedded, dual-sided BGA substrates.

Mercury Systems Chiplets

Mercury Systems is working to lead chiplet technology transfer from Silicon Valley to the DIB using its close collaboration with leading companies in the semiconductor industry. Its SHIP program with Intel will hopefully result in chiplet module fabrication access for the DoD through its DIB suppliers.

Mercury’s vision of a chiplet-based storefront is shown in Figure 8.

Figure 8: Mercury Systems chiplet storefront vision.

But before this can happen, Mercury sees the need for:

  • A mature chiplet ecosystem: The industry should continue to work towards standardization of chip-to-chip communications to enable a sustainable business model
  • Onshore access to state-of-the-art interposers and substrates: Build up onshore manufacturers that can support lower volumes and high mix for the DoD while reducing cycling time.
  • Process design kit for package assembly: Automated tools for customers to select from a library of chiplets to create producible SiPs.
  • Device enablement and support: Sustainable business model that supports diversity of chipletized architectures for different consumers.

TSMC 3DFabric Alliance

TSMC has announced the “3DFabric Alliance” to give partner companies early access to 3D silicon stacking and advanced packaging technologies that offer interoperable solutions that will enable quick development and verification of multi-chiplet Sip’s that use 2.5D and 3D packaging.

TSMC 3DFabric is its family of 3D silicon stacking and advanced packaging technologies. Reportedly, 19 members have joined the 3DFabric Alliance including Micron, Samsung, SK Hynix, ASE, Siliconware, Amkor, Ibiden, and Unimicron.

3DFabric Alliance

Figure 6: The 3D Fabric Alliance represents the entire supply chain from EDA through testing.

TSMC’s 3DFabric consists of both front-end and back-end technologies. Front-end technologies include TSMC’s System on Integrated Chips (SoiC). TSMC backend technologies include the CoWoS and InFO family of packaging technologies.

TSMC envisions that this will make it easier for small and mid-size companies that rely heavily on 3rd party IP/designs, working with EDA software from Ansys Cadence, Synopsys, and Siemens, to design compatible chiplets.  Companies that do not have their own design engineers will be able to order the design of the whole SiP or individual chiplets,  and then update their product over time without needing to redesign everything.

For all the latest on Advanced Packaging stay linked to IFTLE………………………

Phil Garrou

Dr. Philip Garrou is a subject matter expert for DARPA and runs his consulting company…

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