Fig. 1. Chiplet design and heterogeneous integration packaging. (a) Chip partition and heterogeneous integration (driven by cost and technology optimization). (b) Chip split and heterogeneous integration (driven by cost and yield). (c) Multiple system and heterogeneous integration with thin-film layers (2.1D). (d) Multiple system and heterogeneous integration with TSV-less interposer (2.3D). (e) Multiple system and heterogeneous integration with TSV interposer (2.5D). (c) – (e) Driven by performance and form factor. (Modified from Figure 1 of TSMC IEEE/ECTC2021 paper, pp. 130–135.)