SEMI ASMC 2019: Heterogeneous Integration Enters the Mix

SEMI ASMC 2019: Heterogeneous Integration Enters the Mix

“It’s relatively easy to build a fancy new transistor in the lab, but in order to replace what we’re doing today, you need to be able to put billions on a chip, at a reasonable cost, with high reliability and almost no defects. It is very difficult. That makes it all the more important to pursue other ways of making better computers.”

Linley Gwennap, in The Economist, March 2016.

“It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected. The availability of large functions, combined with functional design and construction, should allow the manufacturer of large systems to design and construct a considerable variety of equipment both rapidly and economically.”

G. Moore, “Cramming more components onto integrated circuits”, Electronics, vol. 38, no. 8, 1965.

The Setting: ASMC 2019

The SEMI Advanced Semiconductor Manufacturing Conference convened its 30th annual meeting the week of 06 May 2019 in Saratoga Springs, NY. Continuing to offer outstanding opportunities to share and openly discuss innovative semiconductor manufacturing ideas for both leading-edge technologies and also for trailing-edge, but still vital, mature wafer fabs, ASMC 2019 brought together semiconductor manufacturers, equipment and materials suppliers, and members of academia as conference paper authors, presenters, panelists, and attendees. The conference, sponsored and organized by SEMI, with technical sponsorship from the IEEE Electron Devices Society (EDS) and the IEEE Electronics Packaging Society (EPS), included a healthy amount of heterogeneous integration content this year, warranting a closer look here by 3D InCites.

(For our take on SEMI ASMC 2019 overall, please see “Heterogeneous Integration Component Flavors SEMI ASMC 2019,” Part 1 of our ASMC 2019 report.)

Prominent this year at ASMC 2019 was the very well-received tutorial, “System Level Heterogeneous Integration Will Drive Fundamental Change in Manufacturing,” taught by Bill Bottoms, Ph.D., Co-Chair of the IEEE Heterogeneous Integration Roadmap effort, a tutorial which tied very nicely to ASMC’s ongoing collaboration with IEEE EPS.

ASMC 2019 also featured an engaging panel discussion on “Time to Yield vs. Time to Productivity: What Matters Most in the Age of More than Moore?” Panelists for this session were five notable experts from along the semiconductor supply chain: Shiva Rai, Ph.D., Strategic Marketing Manager, 200mm Equipment Product Group (EPG), Applied Materials; Douglas A. Lawson, Executive Vice President – Corporate Marketing, Axcelis Technologies; Deb Leach, Vice President – Global Sourcing and Supply Chain, GLOBALFOUNDRIES; David Gross, Sr. Director – Manufacturing Technology, SkyWater Technology; and (can we think of her as our own? Or at least as a very kindred spirit?) Jan Vardaman, President, TechSearch International.

Choosing the Low Hanging Fruit

Looking back at my notes to self, written while Bill Bottoms worked through his heterogeneous integration tutorial, the thought that still strikes me hard today is this: Bill’s tutorial was essentially one that, in the end, was a bridge of sorts bringing two worlds together – the semiconductor front-end manufacturing world, the nurturing of which has been ASMC’s principal raison d’être for three decades now, and the advanced packaging world, itself containing an annual circuit of conferences where we hear insights from the leading edge. (Thanks for letting me borrow your blog title, Phil.)

ASMC 2019What happens then when you have a couple of prominent semiconductor device packaging / heterogeneous experts preach to a (relatively) new choir?

You will have heads nodding around the room, as Bill did, nods acknowledging how much sense it makes that heterogeneous integration will soon be replacing Moore’s Law scaling as the “Low Hanging Fruit” in the drive to maintain the pace of continued innovation in semiconductor device fabrication, while continuing to reap the benefits of more system performance for a given level of cost.

Moore’s Law, after all, was an observation more about the economics of transistor fabrication than it was about the technology of same.

Getting Down to Business

One of the many things we like and respect about Jan Vardaman and her approach to market analysis is that it’s first and foremost always about the business with her. The macroeconomy, and its trends up or down, drive our business more than anything new from the semiconductor R&D labs might. You know where Jan’s coming from right off reading her newsletters, and we knew that again right off in Jan’s prepared remarks for the ASMC 2019 panel discussion.

Briefly, Jan proposed that, from where we sit in mid-2019, it is clear that the economic advantages of silicon scaling are gone as a result of the high cost of moving to next the few silicon nodes. Next-gen process node costs are high as a result of several important factors, including the high cost of device design, the high cost of the resulting mask set, and the high cost of the advanced node fab processes, particularly now, with only a limited number of foundries, and a limited number of customers, available to produce integrated circuits at the most advanced process nodes in any kind of quantity volume.

How to remedy this situation? Per Jan, smart packaging provides an opportunity to achieve economic advantages lost as a result of the end of pure Moore’s Law silicon scaling. Assembly of Known Good Parts (Known Good Die, KGD) is key! And, co-design of the silicon device itself and its package is essential to maximize overall yield and, hence, make the economics come out right.

Cue further head nods.

The Economist is an excellent magazine, and in recent coverage by it of our industry, we can read how “It’s relatively easy to build a fancy new transistor in the lab,’ says Linley Gwennap, an analyst. ‘But in order to replace what we’re doing today, you need to be able to put billions on a chip, at a reasonable cost, with high reliability and almost no defects. I hate to say never, but it is very difficult.’ That makes it all the more important to pursue other ways of making better computers.” (Emphasis mine.)

A Word about AI

SEMI ASMC 2018 was much about AI. (See “Nothing Artificial About Pairing Human Intelligence with Machine-Based Smart Manufacturing.”) AI / Smart Manufacturing offers a very reasonable approach toward achieving the “reasonable cost” we need to maintain in advanced semiconductor device manufacturing. Add heterogeneous integration to the technology mix, as we did at SEMI ASMC 2019, and you are looking to come out a winner in the cost-effective manufacturing of ever more complex silicon-based electronic systems, rapidly, and economically.

From Wexford, PA, thanks for reading.

~PFW