Heterogeneous Integration Calls for Increased Materials Reliability

Heterogeneous Integration Calls for Increased Materials Reliability

Dr. Andy C. Mackie, PhD, Indium Corporation

Automotive reliability is a pivotal concern for heterogeneous integration technologies, especially as emerging mission profiles for electric and autonomous vehicles push component lifetimes out by two to three times or more over standard testing regimes. There has been an increasing realization of the importance of chip-package interaction (CPI) as a source of reliability issues in semiconductor assembly. Pinning it down to a single date as the key event, the release of JEDEC JEP156A in March 2018, was a good start in this direction, as it shows a major deviation from the old but still useful Arrhenius/activation energy kinetics models.

Exacerbating the problem is the fact that coreless and thin substrates, thin (2.5D) interposers, and large thinned die have become prevalent in the advanced processor market; there is no single “solid/inflexible” part of the package against which everything else moves. Therefore, the thermal and mechanical stresses present are mutually interdependent and advanced stress modeling and increased understanding of chip-package interaction (CPI) failure mechanisms will be needed.

Heterogeneous integration is here to stay for a few reasons. First, it allows a more modularized approach to system design. Rather than original equipment manufacturers (OEMs) having to ask subcontractors for a specific component or a named device, they can provide a pad layout design and desired functionality and device dimension to their suppliers and ask for that in 18 months.

Secondly, there is no longer a need to rely on specialty system-on-chips (SoCs) so you don’t have the headache of building mixed technologies (like Si and III/V) in the same tool. At SMC 2018, Micron’s John Smythe of Micron put this as “running peanut butter in a chocolate fab.” Finally, if dies are built separately then packaged together, well-characterized fabrication processes will lead to high-yield for individual die; and known-good-die are then used in the final assembly.

Deca Technologies’ M-Series with Adaptive Patterning.

When it comes to wafer-level packaging (WLP) and panel-level packaging (PLP), there are still many issues in fan-out PLP co-planarity for larger packages. The need for technologies such as Deca Technologies Adaptive Patterning™ pad registration software is a tacit acknowledgment that polymer cure in these advanced packages needs much more attention than is presently being given. We can expect to see near-term developments in modeling of the polymer curing process, and specialty heating systems being developed as a result, especially for the huge panels (>50x50cm) being discussed in various consortia. Higher frequency RF devices will be especially sensitive to any deviation from the original I/O layout. For ball-attach on these packages, specialty fluxes have been developed that eliminate many of the emerging failure modes seen with the thin copper traces on the redistribution layer.

The use of wide I/O memory stacks on 2.5D substrates for advanced processor applications needs strong, reliable solder joints. Although the memory dies themselves are being increasingly stacked using non-conductive film by Southeast Asia memory manufacturers, a very low-residue no-clean flip-chip flux is now extensively being used for memory stack attach onto the 2.5D interposer.