Archives October 2016 - 3D InCites

First-Mover Advantage: Fan-Out Panel Level Packaging at IWLPC 2016

First-Mover Advantage: Fan-Out Panel Level Packaging at IWLPC 2016

“It is better to be first than it is to be better.” (Ries and Trout, in The 22 Immutable Laws of Marketing.) Or is it “Fast Followers Not First Movers Are The Real Winners?” Fan-Out Wafer Level Packaging has built up such a head of steam this year (see “iPhone 7: Apple Charts a Strategic Course by Selecting TSMC’s inFO Platform”) that backwards reels the mind thinking about what come... »

iPhone 7: Apple Charts a Strategic Course by Selecting TSMC’s inFO Platform

iPhone 7: Apple Charts a Strategic Course by Selecting TSMC’s inFO Platform

Each year, Apple integrates more and more innovative technologies in its iPhone products. This year, with the new iPhone 7 and its A10 processor, the leading company is the first organization to bring out package-on-package (PoP) wafer-level packaging (WLP) at the consumer scale. Apple underwent a strategic change by selecting TSMC’s new integrated fan-out PoP (inFO-PoP) technology for its new A... »

Pasadena offers Roses and Technology

Pasadena offers Roses and Technology

California’s Pasadena is well known for the New Year Rose Parade and the Rose Bowl. There is no doubt: It takes commitment and organizational talent to make these events successful for 100+ years, and encourage every contributor to prepare and execute successful events every year. Last week’s International Microelectronics Assembly and Packaging Solutions Conference (iMAPS) in Pasadena’s Con... »

At the 2016 S3S Conference, 3D Integration is Bringing Sexy Back

At the 2016 S3S Conference, 3D Integration is Bringing Sexy Back

The IEEE S3S Conference (shorthand for the IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference; quite a mouthful, I know!) is an annual gathering of an intimate crowd (generally 100-125 attendees) that for 35 years has been the premier meeting of engineers and scientists dedicated to current trends in Silicon-On-Insulators (SOI) technology. A parallel 3D integration track was a... »

3D TSVs are essential for Heterogeneous Integration, HPC and High-end Memory

3D TSVs are essential for Heterogeneous Integration, HPC and High-end Memory

This year again, both market segments, high end, and low end, are the main targets of through silicon via (TSV) technology providers. In its latest advanced packaging technology and market analysis entitled 3DIC and 2.5D TSV Interconnect for Advanced Packaging: 2016 Business Update report, Yole Développement (Yole) announces, high volume production started: 3D TSV is a reality, especially in the ... »

Image Courtesy of TSMC Ltd.

TSMC’s OIP Symposium 2016

After a fairly long vacation it’s very hard to get back to work. That’s why I was really glad that this year’s OIP Symposium helped me – right after touring Europe for 3 weeks – to finding my groove again. Allow me to share some of my observations at and thoughts about the Symposium, from my “More-than-Moore EcoSystem builder” perspective. The collaborative innovation programs TSMC ... »

Fraunhofer EMFT Signs Agreement to Implement ZiBond and DBI Technologies in MEMS Applications

Invensas Corporation, a wholly owned subsidiary of Tessera Technologies, Inc., (Nasdaq: TSRA) has announced that Fraunhofer EMFT has signed a new license agreement to incorporate ZiBond® and Direct Bond Interconnect (DBI®) technologies into their portfolio of foundry services. This agreement expands Fraunhofer EMFT’s world-class MEMS manufacturing capabilities with the most advanced 3D integr... »